AMD XILINX T2 Telco, User Manual

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Chapter 3
Pin Mapping
This chapter presents the pin mapping for the ZU48DR Zynq
®
Ult™ RFSoC on the T2
card.
PCIe Interface
The PCIe ® interface on the T2 card has 16 lanes and can operate in Gen 3 x16 mode or Gen 4
x8x8 bifurcated mode.
Using the PCIe Interface
• The PCIe interface is supported with a dedicated IP block that must be instantiated in the
design.
• PCIe lane reversal is in use.
• The server slot used with the T2 card must be a x16 capable and configured correctly for card
detection and use. The Gen 4 x8x8 mode of operation requires x8 bifurcation to be enabled,
whereas Gen 3 x16 requires x16 mode.
PCIe Interface Pins
The following table summarizes the ZU48DR PCIe interface pin map.
Table 1: PCIe Interface Pin Map
Pin Number Signal Name Description I/O
W34 PCIE_RF_LOWER_REFCLK_N PCIe Lower Diff Clock (N) I
W33 PCIE_RF_LOWER_REFCLK_P PCIe Lower Diff Clock (P) I
P32 PCIE_RF_UPPER_REFCLK_N PCIe Upper Diff Clock (N) I
P31 PCIE_RF_UPPER_REFCLK_P PCIe Upper Diff Clock (P) I
AJ13 PCIE_RF_PERST_LS PCIe Reset I
AA39 PCIE_RX0_N PCIe RX Data 0 (N) I
AA38 PCIE_RX0_P PCIe RX Data 0 (P) I
W39 PCIE_RX1_N PCIe RX Data 1 (N) I
W38 PCIE_RX1_P PCIe RX Data 1 (P) I
Chapter 3: Pin Mapping
UG1496 (v1.0) June 15, 2022 www.xilinx.com
T2 Telco Accelerator Card User Guide 9
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