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AMD SP5100 Databook
44409 Rev. 1.70 October 10
16
SP5100 Power on Sequence and Timing
S3
S3
S0
VBA
T
VBAT
RTC clock
+3.3V_S5
+1.2V_S5
RSMRST#
S0 power rails
SB PWRGOOD
A_RST#
KBRST#
T8B
PCIRST#
T10
PCIE_RCLKP/N
PCICLK[5:0]
NB_PWRGD
T7
T7A
LDT_PG
(See Note 5)
T11
T8A
T9
T9A
LDT_STP#
(Note 8)
Wake Event
SLP_S3#
T13
T8D
LDT_RST#
ALLOW_LDTSTP
WAKE#
PWR_BTN#
PS PWOK
T13A
T7B
(See Note 4)
SLP_S5#
GND
GND
GND
GND
GND
T8C
System clocks
(See Note 1 & 2)
T9B
Figure 3-2: SP5100 S3/S0 Power Up/Down Sequence