AMD Elan SC520, User Manual, Page: 54 / 444

Pin Information
2-12 Élan™SC520 Microcontroller User’s Manual
JTAG Boundary Scan Test Interface
JTAG_TCK — I Test Clock is the input clock for test access port.
JTAG_TDI — I Test Data Input is the serial input stream for input data. This pin has
a weak internal pullup resistor. It is sampled on the rising edge of
JTAG_TCK. If not driven, this input is sampled High internally.
JTAG_TDO — O/TS Test Data Output is the serial output stream for result data. It is in the
high-impedance state except when scanning is in progress.
JTAG_TMS — I Test Mode Select is an input for controlling the test access port. This
pin has a weak internal pullup resistor. If it is not driven, it is sampled
High internally.
JTAG_TRST — I JTAG Reset is the test access port (TAP) reset. This pin has a weak
internal pulldown resistor. If not driven, this input is sampled Low
internally and causes the TAP controller logic to remain in the reset
state.
AMDebug Interface
BR/TC — I Break Request/Trace Capture requests entry to AMDebug
technology mode. The AMDebug technology serial/parallel interface
can reconfigure this pin to turn instruction trace capture on or off.
CMDACK — O Command Acknowledge indicates command completion status. It is
asserted High when the in-circuit emulator logic is ready to receive
new commands from the host. It is driven Low when the in-circuit
emulator core is executing a command from the host and remains Low
until the command is completed.
STOP/TX — O Stop/Transmit is asserted High on entry to AMDebug mode. During
normal mode, this is set High when there is data to be transmitted to
the host (during operating system/application communication).
TRIG/TRACE — O Trigger/Trace triggers event to logic analyzer (optional, from Am5
x
86
CPU debug registers).The AMDebug technology serial/parallel
interface can reconfigure this pin to indicate the trace on or off status.
System Test
CF_DRAM [WBMSTR2]
{CFG2} O Code Fetch SDRAM, during SDRAM reads, provides code fetch
status. When Low, this indicates that the current SDRAM read is a
CPU code fetch demanded by the CPU, or a read prefetch initiated
due to a demand code fetch by the CPU. When High during reads, this
indicates that the SDRAM read is not a code fetch, and it could have
been initiated by the CPU, PCI master, or the GP bus GP-DMA
controller, either demand or prefetch. During SDRAM write cycles this
pin provides an indication of the source of the data, either GP-DMA
controller/PCI bus master or CPU. When High, this indicates that
either a GP bus DMA initiator or an external PCI bus master
contributed to the current SDRAM write cycle (the CPU may also have
contributed). A Low indicates that the CPU is the only master that
contributed to this write cycle.
CF_ROM_GPCS [WBMSTR0]
{CFG0} O Code Fetch ROM/GPCS provides an indication that the CPU is
performing a code fetch from ROM (on either the GP bus or SDRAM
data bus), or from any GPCSx pin. When Low during a read cycle (as
indicated by either GPMEMRD or ROMRD), the CPU is performing a
code fetch from ROM or a GP bus chip select. At all other times
(including writes), this signal is High.
DATASTRB [WBMSTR1]
{CFG1} O Data Strobe is a debug signal that is asserted to allow the external
system to latch SDRAM data. This can be used to trace data on the
SDRAM interface with an in-circuit emulator probe or logic analyzer.
Table 2-2 Signal Descriptions (Continued)
Signal
Multiplexed
Signal Type Description