AMD Elan SC520, User Manual, Page: 381 / 444

System Test and Debugging
Élan™SC520 Microcontroller User’s Manual 24-7
24.4.2 Write Buffer Test Mode
Write buffer test mode identifies which bus owners (Am5
x
86 CPU, PCI bus master, or GP-
DMA controller) have contributed to the current SDRAM write cycle, and which bus owner
is requesting the current SDRAM read cycle.
The ÉlanSC520 microcontroller implements a 32-rank First-In-First-Out (FIFO) write buffer
for improved memory performance. The write buffer also supports write merging and write
collapsing. Therefore, each of the 32-bit ranks and each byte within the rank can be written
by either the Am5
x
86 CPU, PCI bus masters, or the GP-DMA controller. For example, byte
0 and byte 1 of a write buffer rank can be written by the Am5
x
86 CPU, byte 2 of the same
rank can be written by a PCI bus master, and byte 3 of the same rank can be written by
the GP-DMA controller.
Although this will result in improved performance of the SDRAM subsystem, it can be
confusing when attempting system debugging with a logic analyzer, because it is impossible
to identify the source of SDRAM write cycles from the normal SDRAM interface alone. (For
more information on the write buffer, see Chapter 11, “Write Buffer and Read Buffer”.)
When write buffer test mode is enabled via the WB_TST_ENB bit in the SDRAM Control
(DRCCTL) register (MMCR offset 10h), the WBMSTR2
± WBMSTR0 pins indicate whether
the Am5
x
86 CPU, PCI bus master, GP-DMA controller, or a combination of these has written
into a particular rank of the write buffer.
24.4.2.1 Using the Write Buffer Test Mode Interface
Sampling the WBMSTR2
±
WBMSTR0 pins for write buffer debugging requires external
decoding of the SDRAM interface signals to determine when write cycles are occurring on
the SDRAM interface. To provide useful information about the cycle, the BA1–BA0 and
MA12–MA0 SDRAM address bus must be demultiplexed to provide the full 28-bit memory
address, and the SRASx, SCASx, and SWEx command signals must be sampled to
differentiate reads, writes, refresh cycles, etc.
Figure 24-3 shows WBMSTR2 ± WBMSTR0 timing during a SDRAM write cycle. The trace
information is available one clock before the clock edge where the command is driven to
the SDRAM. This guarantees sufficient setup so the trace information can be captured on
the clock edge where the SDRAM command is sampled. It is the responsibility of the
monitoring equipment to capture the WBMSTR2
±
WBMSTR0 trace signals information at
the appropriate time and cycle type. This can be accomplished by monitoring the SDRAM
interface pins and decoding the SDRAM cycle type for the programmed SDRAM timing.
See Chapter 10, “SDRAM Controller”, for details on the ÉlanSC520 microcontroller’s
address multiplexing scheme and SDRAM timing and signaling.
Determining when the data is valid during SDRAM read cycles requires knowledge of the
SDRAM timing configuration, such as CAS latency, etc. See “SDRAM Read Cycle in Write
Buffer Test Mode” on page 24-8. For writes, the data is available at the time of the write.