AMD Elan SC520, User Manual, Page: 341 / 444

Real-Time Clock
Élan™SC520 Microcontroller User’s Manual 20-7
20.5 OPERATION
Programs can retrieve time and calendar information from the RTC by reading the
appropriate RTC index registers. Programs can also change the time, calendar, and alarm
information in the RTC by writing to these registers.
The RTC executes an update cycle once per second, assuming that the OSC_CTL bit field
in the RTC Control A (RTCCTLA) register (RTC index 0Ah) has been set to 010b and that
the SET bit in RTC Control B (RTCCTLB) register has been cleared. When the SET bit is
1, all updates are disabled, and the program can initialize the time and date registers.
With a 32.768-kHz time base, the update cycle takes 1984
µ
s
. If a program reads these
RAM locations before the update is complete, the output is undefined. The Update-In-
Progress (UIP) status bit is set in the RTC Control A (RTCCTLA) register during this time.
There are three ways to handle nonavailability during an RTC update.
■
Use the update-ended interrupt—If enabled, this interrupt occurs after every update
cycle. This means that over 998 ms are available to read the time and date registers.
■
Use the Update-in-Progress bit (UIP) in RTC Control A (RTCCTLA) register—The UIP
bit changes once per second. The update cycle begins 244
µ
s after the UIP bit goes
high. This means that, if a 0 is read on the UIP bit, there are at least 244
µ
s before the
time or calendar data will be changed. If a 1 is read in the UIP bit, the time or calendar
data may not be valid. Note that the time allocated to read time or calendar data should
not exceed 244
µ
s.
■
Use a periodic interrupt to determine if an update cycle is occurring.
Note that, to ensure correct data, the time should not be set on the last day of the month
within two seconds of the rollover to the next day.
20.5.1 Configuration Information
20.5.1.1 Configuring the Hour Format
The 12/24 Hour Mode Select (HOUR_MODE_SEL) bit in the RTC Control B (RTCCTLB)
register (RTC index 0Bh) establishes whether the hour locations represent 1-to-12 or 0-to-
23. The HOUR_MODE_SEL bit can not be changed without re-initializing the RTC Current
Hour (RTCCURHR) register (RTC index 04h) and the RTC Alarm Hour (RTCALMHR)
RTC Control A RTCCTLA 70h/71h
Index 0Ah Update status, divider chain control, and
periodic interrupt rate selection
RTC Control B RTCCTLB 70h/71h
Index 0Bh Update override (SET); periodic interrupt, alarm
interrupt, and update-ended interrupt enables;
date mode, 24/12 hour control, and daylight
saving enable
RTC Status C RTCSTAC 70h/71h
Index 0Ch Interrupt request, periodic interrupt, alarm
interrupt, and update-ended interrupt flags
RTC Status D RTCSTAD 70h/71h
Index 0Dh RTC power status (BBATSEN)
General-Purpose CMOS
RAM (114 bytes) RTCCMOS 70h/71h
Index 0E–
7Fh General-purpose CMOS RAM bytes
Table 20-3 Real-Time Clock Registers—RTC Indexed (Continued)
Register Mnemonic I/O Address Function