AMD Elan SC520, User Manual, Page: 274 / 444

GP Bus DMA Controller
14-8 Élan™SC520 Microcontroller User’s Manual
14.5 OPERATION
The GP-DMA controller on the ÉlanSC520 microcontroller supports the following features.
■
Only fly-by GP-DMA transfers are supported. A fly-by transfer is a transfer in which the
data is moved from an I/O device or a memory-mapped I/O device to SDRAM (GP-DMA
write), or from SDRAM to an I/O device or a memory-mapped I/O device (GP-DMA read)
in a single transaction.
■
Memory-to-memory (i.e., SDRAM-to-SDRAM) and I/O-to-I/O (peer-to-peer on the GP
bus) transfers are not supported.
■
Transfer modes supported: single, block, and demand
■ Transfer types supported: read, write, and verify
14.5.1 GP-DMA Transfers
Because the ÉlanSC520 microcontroller also supports the standard PC/AT system
architecture, the method for DMA transfer complies with the Industry Standard Architecture
(ISA) specifications. The default polarities of GPDRQx and GPDACKx are active High and
Low respectively, but they can be programmed differently.
The following general rules apply to GP-DMA transfers on the ÉlanSC520 microcontroller:
■
The GP-DMA initiator is the I/O device that asserts GPDRQx. This is always an external
I/O device (or memory -mapped I/O device) residing on the GP bus, or the internal UART
serial ports, and can be either 8 bits or 16 bits. Note that the internal UARTs must be
programmed as 8-bit channels.
■
The GP-DMA target is always system memory (SDRAM). Table 14-4 shows the possible
GP-DMA initiators and targets.
Master DMA Controller Reset
Slave DMA Controller Reset
MSTDMARST
SLDMARST
00DAh
000Dh
GP-DMA controller reset
Master DMA Controller Temporary
Slave DMA Controller Temporary
MSTDMATMP
SLDMATMP
00DAh
000Dh
Preserves PC/AT compatibility
Master DMA Mask Reset
Slave DMA Mask Reset
MSTDMAMSKRST
SLDMAMSKRST
00DCh
000Eh
Mask register reset to activate the
associated GP-DMA channels
Master DMA General Mask
Slave DMA General Mask
MSTDMAGENMSK
SLDMAGENMSK
00DEh
000Fh
GP-DMA channel masks
General-Purpose Registers
General Registers GPDMAGR0
GPDMAGR1
GPDMAGR2
GPDMAGR3
GPDMAGR4
GPDMAGR5
GPDMAGR6
GPDMAGR7
GPDMAGR8
0080h,
0084h–
0086h,
0088h,
008Ch–
008Fh General-purpose R/W registers
Table 14-3 GP-DMA Controller Registers—Direct-Mapped (Continued)
Register Mnemonic
I/O
Address
Function