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Write Buffer and Read Buffer
Élan™SC520 Microcontroller User’s Manual
11-9
Figure 11-5
Write Buffer Read-Merging Example
11.5.1.3
Write Buffer Watermark
The write buffer provides a watermark setting of either 8, 16, 24 or 28 doublewords. As
data is written into the write buffer, a new rank of storage is allocated, provided that write-
merging or collapsing is not taking place. When a write cycle resulting in a rank being
allocated takes place that exceeds the watermark setting, the write buffer requests service
from the SDRAM controller to initiate write transfers to SDRAM.
■
A higher watermark setting (i.e., 28 doublewords) allows the write buffer to acquire more
master write data prior to requesting SDRAM controller attention than a lower watermark
setting. If a large amount of incomplete doubleword writes (i.e., byte, word, or three byte
write transfers) is expected from either the Am5
x
86 CPU, PCI, or GP-DMA, a higher
watermark setting allows the write buffer to fill higher prior to requesting SDRAM service,
resulting in a greater chance of write data merging or collapsing.
■
A lower watermark setting can be used for applications that require more complete
doublewords, and where merging/collapsing of data is less likely. This causes the write
buffer to request SDRAM service at a lower threshold, thus reducing the chance of filling
the write buffer.
The write buffer watermark setting can be configured with the WB_WM bit in the SDRAM
Buffer Control (DBCTL) register (MMCR offset 40h). A waterrmark of 16 doublewords is
recommended.
78
56
D[7:0]
D[15:8]
D[23:16]
D[31:24]
12
34
CD
EF
FBC
0
000
0
000
000
5
678
000
CDEF
A
0
0
A[27:2]
BE[3:0]
Master
SDRAM
Write Buffer (Address Segment)
Write Buffer (Data Segment)
Re
a
d
Da
ta
Wr
ite
D
a
ta
Add
res
s
EE001122
Read
Merge
Logic
EE00CDEF
xxxxCDEF
Notes:
This example illustrates a 32-bit master read of address A000000h, which causes a read hit in
the write buffer. This causes the lower data word from the write buffer to be merged with the upper
data word from SDRAM, to return the entire doubleword to the requesting master.
00
AA
CC
00
00
FF
FE
55
11
A0
000
00
Summary of Contents for Elan SC520
Page 1: ...lan SC520 Microcontroller User s Manual Order 22004A...
Page 4: ...iv lan SC520 Microcontroller User s Manual...
Page 28: ...Introduction xxviii lan SC520 Microcontroller User s Manual...
Page 42: ...Architectural Overview 1 14 lan SC520 Microcontroller User s Manual...
Page 78: ...System Initialization 3 22 lan SC520 Microcontroller User s Manual...
Page 108: ...Clock Generation and Control 5 10 lan SC520 Microcontroller User s Manual...
Page 118: ...Reset Generation 6 10 lan SC520 Microcontroller User s Manual...
Page 148: ...System Arbitration 8 24 lan SC520 Microcontroller User s Manual...
Page 214: ...SDRAM Controller 10 36 lan SC520 Microcontroller User s Manual...
Page 230: ...Write Buffer and Read Buffer 11 16 lan SC520 Microcontroller User s Manual...
Page 288: ...GP Bus DMA Controller 14 22 lan SC520 Microcontroller User s Manual...
Page 316: ...Programmable Interval Timer 16 8 lan SC520 Microcontroller User s Manual...
Page 328: ...Software Timer 18 4 lan SC520 Microcontroller User s Manual...
Page 346: ...Real Time Clock 20 12 lan SC520 Microcontroller User s Manual...
Page 360: ...UART Serial Ports 21 14 lan SC520 Microcontroller User s Manual...
Page 414: ...AMDebug Technology 26 8 lan SC520 Microcontroller User s Manual...