AMD Elan SC520, User Manual, Page: 219 / 444

Write Buffer and Read Buffer
Élan™SC520 Microcontroller User’s Manual 11-5
11.5.1 Write Buffer
The ÉlanSC520 microcontroller’s SDRAM controller contains 32 4-byte write data buffers.
The write buffer provides benefits beyond that of a standard posting FIFO. A standard FIFO
blindly posts data without knowledge of data that already exists within the FIFO. The write
buffer is more efficient in that each write access is snooped.
The snoop function is used to determine if data associated with the current address already
exists in the FIFO. This feature allows write data to be merged or collapsed with data that
already exists in the write buffer. This results in a reduced number of overall writes to
SDRAM for contiguous partial doubleword writes and also more efficiently utilizes the FIFO
storage. The snoop capability also provides the read-merging function to more efficiently
handle data coherency overhead. It does this by not requiring a total write buffer flush before
servicing a read cycle (which would ordinarily be required by a standard FIFO that does
not provide snooping).
The write buffer provides the following benefits:
■
Zero wait state write data posting (to a non-full buffer), effectively decoupling master
write activity from SDRAM latency
■
Read-around-write support, enhanced by the read-merging function, effectively allowing
the SDRAM controller to give read priority over buffered writes to SDRAM
■
Write-merging and write-collapsing of write data
The read-around-write feature is provided when the write buffer is enabled. It allows read
requests to SDRAM to occur in front of, or around, write buffer requests. Write buffer
requests are due to write data that was posted during previous master write activity and is
migrating to SDRAM. Read-around-write is only functional when the write buffer is enabled.
11.5.1.1 Write Buffer Disabled
When the write buffer is disabled, all write and read traffic generated by any master is
directed around the write buffer directly to SDRAM. Write data is no longer posted, and
read cycles no longer require snooping for data coherency. If the write buffer contained
valid data when it was disabled, it is automatically flushed (by hardware) to SDRAM as a
top priority before SDRAM is free to service any subsequent requests. This guarantees
data coherency. Should any master try a read or write access to SDRAM at this time, the
cycle is stalled (via wait states) until the write buffer flush is complete.
The write buffer can be manually flushed by setting the WB_FLUSH bit in the SDRAM
Buffer Control (DBCTL) register (MMCR offset 40h). Write buffer flush complete status is
available after a manual flush by reading the WB_FLUSH bit.
11.5.1.2 Write Buffer Enabled
When the write buffer is enabled, all write data by all masters are written into the write
buffer. Data are written into SDRAM from the write buffer in FIFO fashion when the SDRAM
controller is free to service the request.
The snoop capability is used to enhance performance for both read and write cycles.
■ Through the use of the snoop feature on write cycles, the write buffer can determine if
data already exists, and, if so, it either write-merges or write-collapses the data. This
enhances write performance through a reduction in the total number of required write
cycles to SDRAM for contiguous writes and also makes better utilization of the physical
storage space of the buffer.