AMD Am186 ES, User Manual, Page: 73 / 192

Chip Select Unit 5-3
overlap must have the same configuration for ready (external ready required or not required)
and the number of wait states to be inserted into the cycle by the processor.
The peripheral control block (PCB) is accessed using internal signals. These internal signals
function as chip selects configured with zero wait states and no external ready. Therefore,
the PCB can be programmed to addresses that overlap external chip select signals if those
external chip selects are programmed to zero wait states with no external ready required.
When overlapping an additional chip select with either the LCS or UCS chip selects, it must
be noted that setting the Disable Address (DA) bit in the LMCS or UMCS register will disable
the address from being driven on the AD bus for all accesses for which the associated chip
select is asserted, including any accesses for which multiple chip selects assert.
The MCS and PCS chip select pins can be configured as either chip selects (normal
function) or as PIO inputs or outputs. It should be noted; however, that the ready and wait
state generation logic for these chip selects is in effect regardless of their configurations
as chip selects or PIOs. This means that if these chip selects are enabled (by a write to the
MMCS and MPCS for the MCS chip selects, or by a write to the PACS and MPCS registers
for the PCS chip selects), the ready and wait state programming for these signals must
agree with the programming for any other chip selects with which their assertion would
overlap if they were configured as chip selects.
Although the PCS4 signal is not available on an external pin, the ready and wait state logic
for this signal still exists internal to the part. For this reason, the PCS4 address space must
follow the rules for overlapping chip selects. The ready and wait-state logic for PCS6–PCS5
is disabled when these signals are configured as address bits A2–A1.
Failure to configure overlapping chip selects with the same ready and wait state
requirements may cause the processor to hang with the appearance of waiting for a ready
signal. This behavior may occur even in a system in which ready is always asserted (ARDY
or SRDY tied High).
Configuring PCS in I/O space with LCS or any other chip select configured for memory
address 0 is not considered overlapping of the chip selects. Overlapping chip selects refers
to configurations where more than one chip select asserts for the same physical address.
5.5 CHIP SELECT REGISTERS
The following sections describe the chip select registers.