AMD Am186 ES, User Manual, Page: 72 / 192

Chip Select Unit 5-2
Except for the UCS chip select, which is active on reset as discussed in Section 5.5.1, chip
selects are not activated until the associated registers have been accessed. (An access is
any write operation and only write operations activate.) For this reason, the chip select
registers should not be read by the processor initialization code until after they have been
written with valid data. The LCS chip select is activated when the LMCS register is accessed,
the MCS chip selects are activated after both the MMCS and MPCS registers have been
accessed, and the PCS chip selects are activated after both the PACS and MPCS registers
have been accessed.
5.2 CHIP SELECT TIMING
The timing for the UCS and LCS outputs has been modified from the original 80C186
microcontroller. These outputs now assert in conjunction with the nonmultiplexed address
bus (A19–A0) for normal memory timing. To allow these outputs to be available earlier in
the bus cycle, the number of programmable memory size selections has been reduced.
The MCS3–MCS0 and PCS chip selects assert with the AD bus.
5.3 READY AND WAIT-STATE PROGRAMMING
The Am186ES and Am188ES microcontrollers can be programmed to sense a ready signal
for each of the peripheral or memory chip select lines. The ready signal can be either the
ARDY or SRDY signal. Each chip select control register (UMCS, LMCS, MMCS, PACS,
and MPCS) contains a single-bit field, R2, that determines whether the external ready signal
is required or ignored. When R2 is set to 1, external ready is ignored. When R2 is set to 0,
external ready is required.
The number of wait states to be inserted for each access to a peripheral or memory region
is programmable. Zero wait states to 15 wait states can be inserted for the PCS3–PCS0
peripheral chip selects. Zero wait states to three wait states can be inserted for all other
chip selects.
Each of the chip select control registers other than the PACS register (UMCS, LMCS,
MMCS, and MPCS) contains a two-bit field, R1–R0, whose value determines the number
of wait states from zero to three to be inserted. A value of 00b in this field specifies no
inserted wait states. A value of 11b specifies three inserted wait states.
The PCS3–PCS0 peripheral chip selects can be programmed for up to 15 wait states. The
PACS register uses bits R3 and R1–R0 for the additional wait states.
When external ready is required (R2 is set to 0), internally programmed wait states will
always complete before external ready can terminate or extend a bus cycle. For example,
if the internal wait states are set to insert two wait states (R1–R0 = 10b), the processor
samples the external ready pin during the first wait cycle. If external ready is asserted at
that time, the access completes after six cycles (four cycles plus two wait states). If external
ready is not asserted during the first wait cycle, the access is extended until ready is
asserted, which is followed by one more wait state followed by t
4
.
The ARDY signal on the Am186ES and Am188ES microcontrollers is a true asynchronous
ready signal. The ARDY pin accepts a rising edge that is asynchronous to CLKOUTA and
is active High. If the falling edge of ARDY is not synchronized to CLKOUTA as specified,
an additional clock period may be added.
5.4 CHIP SELECT OVERLAP
Although programming the various chip selects on the Am186ES microcontroller so that
multiple chip select signals are asserted for the same physical address is not recommended,
it may be unavoidable in some systems. In such systems, the chip selects whose assertions