AMD Am186 ES, User Manual, Page: 68 / 192

Peripheral Control Block 4-8
CLKOUTB can be used as a full-speed clock source in power-save mode.
Bit 10: CLKOUTB Drive Disable (CBD)—When set to 1, CBD three-states the clock output
driver for CLKOUTB. When set to 0, CLKOUTB is driven as an output. This bit is 0 after
processor reset.
Bit 9: CLKOUTA Output Frequency (CAF)—When set to 1, CLKOUTA follows the crystal
input (PLL) frequency. When set to 0, CLKOUTA follows the internal processor frequency
(after the clock divisor). This bit is 0 after processor reset.
CLKOUTA can be used as a full-speed clock source in power-save mode.
Bit 8: CLKOUTA Drive Disable (CAD)—When set to 1, CAD three-states the clock output
driver for CLKOUTA. When set to 0, CLKOUTA is driven as an output. This bit is 0 after
processor reset.
Bits 7–3: Reserved—Read back as 0.
Bits 2–0: Clock Divisor Select (F2–F0)—Controls the division factor when Power-Save
mode is enabled. F2–-F0 is 000b after processor reset. Allowable values are as follows:
4.2 INITIALIZATION AND PROCESSOR RESET
Processor initialization or startup is accomplished by driving the RES input pin Low. RES
must be Low during power-up to ensure proper device initialization. RES forces the
Am186ES and Am188ES microcontrollers to terminate all execution and local bus activity.
No instruction or bus activity occurs as long as RES is active.
After RES is deasserted and an internal processing interval elapses, the microcontroller
begins execution with the instruction at physical location FFFF0h. RES also sets some
registers to predefined values as shown in Table 4-3.
F2 F1 F0 Divider Factor
0 0 0
Divide by 1 (2
0
)
0 0 1
Divide by 2 (2
1
)
0 1 0
Divide by 4 (2
2
)
0 1 1
Divide by 8 (2
3
)
1 0 0
Divide by 16 (2
4
)
1 0 1
Divide by 32 (2
5
)
1 1 0
Divide by 64 (2
6
)
1 1 1
Divide by 128 (2
7
)