AMD Am186 ES, User Manual, Page: 159 / 192

Asynchronous Serial Port 10-13
10.2.5 Serial Port 0/1 Baud Rate Divisor Registers
(SP0BAUD/SP1BAUD, Offset 88h/18h)
Each of the asynchronous serial ports has a baud rate divisor register, so the two ports can
operate at different rates.
These registers (Figure 10-7) specify a clock divisor for the generation of the serial clock
that controls the associated serial port. The baud rate divisor register specifies the number
of internal processor cycles in one phase (half period) of the 16x serial clock.
If power-save mode is in effect, the baud rate divisor must be reprogrammed to reflect the
new processor clock frequency. Since power-save mode is automatically exited when an
interrupt is taken, serial port transmits and receives may be corrupted if the serial port is in
use and interrupts are enabled during power-save mode.
A general formula for the baud rate divisor is:
BAUDDIV =
(Processor Frequency
÷
(16
⋅
baud rate))
The maximum baud rate is 1/16 of the internal processor clock and is achieved by setting
BAUDDIV=0001h. This results in a baud rate of 2500 Kb at 20 MHz, 1562.5 Kb at 25MHz,
2062.5 Kb at 33 MHz, and 1250 Kb at 40 MHz. A BAUDDIV setting of zero results in no
transmission or reception of data.
The serial port receiver can tolerate a 3.0% overspeed and 2.5% underspeed baud rate
deviance.
Table 10-5 Common Baud Rates
Baud
Rate
Divisor Based on CPU Clock Rate
20 MHz 25 MHz 33 MHz 40 MHz
300 4166 5208 6875 8333
600 2083 2604 3437 4166
1050 1190 1488 1964 2380
1200 1041 1302 1718 2083
1800 694 868 1145 1388
2400 520 651 859 1041
4800 260 325 429 520
7200 173 217 286 347
9600 130 162 214 260
19200 65 81 107 130
28800 43 54 71 86
38400 33 40 53 65
56000 22 28 36 45
57600 22 27 35 43
76800 16 20 26 32
115200 10 13 18 22