AMD Am186 ES, User Manual, Page: 111 / 192

Interrupt Control Unit 7-23
7.3.9 Priority Mask Register
(PRIMSK, Offset 2Ah)
(Master Mode)
The Priority Mask register provides the value that determines the minimum priority level at
which maskable interrupts can generate an interrupt.
Figure 7-12 Priority Mask Register
The value of PRIMSK at reset is 0007h.
Bits 15–3: Reserved—Set to 0.
Bits 2–0: Priority Field Mask (PRM2–PRM0)—This field determines the minimum priority
that is required for a maskable interrupt source to generate an interrupt. Maskable interrupts
with programmable priority values that are numerically higher than this field are masked.
The possible values are zero (000b) to seven (111b).
A value of seven (111b) allows all interrupt sources that are not masked to generate
interrupts. A value of five (101b) allows only unmasked interrupt sources with a
programmable priority of zero to five (000b to 101b) to generate interrupts.
Table 7-4 Priority Level
Priority PR2–PR0
(High) 0 0 0 0b
1 0 0 1b
2 0 1 0b
3 0 1 1b
4 1 0 0b
5 1 0 1b
6 1 1 0b
(Low) 7 1 1 1b
15
7 0
0 0 0 0 0 0 0 0 0 0 0 0
PRM2
PRM1
PRM0
0