High-Level Data Link Control (HDLC)
15-6
Am186™CC/CH/CU Microcontrollers User’s Manual
Table 15-2
HDLC Register Summary
Offset
1
Register
Mnemonic
2
Register Name
Description
00h
HxCON
HDLC Channel Control
Sets operating modes for both the transmitter
and receiver.
02h
HxTCON0
HDLC Channel Transmit Control 0
Sets operating modes for transmitter.
04h
HxTCON1
HDLC Channel Transmit Control 1
06h
HxRCON0
HDLC Channel Receive Control
Sets operating modes for receiver.
08h
HxRCON1
HDLC Channel Receive Max Length
Sets maximum length for received frame.
Should never be set to 2 or less.
0Ah
HxSTATE
HDLC Channel Status
Contains read-only status for transmitter and
receiver.
0Ch
HxISTAT0
HDLC Channel Interrupt Status 0
Contains status for transmitter and receiver. All
bits can generate an interrupt if not masked off
in HxIMSK0.
0Eh
HxIMSK0
HDLC Channel Interrupt 0 Mask
Mask register for HxISTAT0. When a mask bit
is 0 (the reset value), the corresponding
interrupt is masked off.
10h
HxISTAT1
HDLC Channel Interrupt Status 1
Contains status for receiver. All bits can
generate an interrupt if not masked off in
HxIMSK1.
12h
HxIMSK1
HDLC Channel Interrupt 1 Mask
Mask register for HxISTAT1. When a mask bit
is 0 (the reset value), the corresponding
interrupt is masked off.
14h
HxTD
HDLC Channel Transmit FIFO Data
Contains data for transmission.
16h
HxRD
HDLC Channel Receive FIFO Data
Contains data from receive. After all the data
has been read, this register contains the three
bytes of status for the frame, as described
below.
H
x
RFS1
HDLC Channel Receive Frame Status 1
Contains the first byte of status: the least
significant byte of the length of the received
frame.
HxRFS2
HDLC Channel Receive Frame Status 2
Contains the second byte of status: the most
significant byte of the length of the received
frame.
HxRFS3
HDLC Channel Receive Frame Status 3
Contains the third byte of status: the status for
the frame and which address was matched.
18h
HxRDP
HDLC Channel Receive FIFO Data
Peek
Copy of HxRD register that does not change
when read.
1Ah
HxSFCNT
HDLC Channel Short Frame Counter
Contains the count of the number of frames
that were discarded because they were
smaller than the minimum receive length.
Reading this register resets it to 0.
1Ch
HxSFCNTP
HDLC Channel Short Frame Counter
Peek
Copy of HxSFCNT register that does not
change when read.
1Eh
HxMACNT
HDLC Channel Mismatch Address
Counter
Contains the count of the number of frames
that were discarded because they did not
match any of the address registers. Reading
this register resets it to 0.
Summary of Contents for Am186 CC
Page 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Page 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Page 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Page 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Page 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Page 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Page 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Page 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Page 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...