Synchronous Serial Port (SSI)
14-8
Am186™CC/CH/CU Microcontrollers User’s Manual
Figure 14-5
SSI Single-Transmit, Multiple-Receive with SDEN as External Device Enable
14.5.4
Software-Related Considerations
The SSI interface allows for a variety of software and hardware protocols:
■
Signaling a read/write: In general, software uses the first write to the SSI to transmit
an address or count to the peripheral. This value can include a read/write flag in the
case where the device supports both reads and writes.
■
Using SSTXD1 as an address register: The SSTXD1 register can be an address
register that holds the value of the last address accessed, and the SSTXD0 register can
be the data transmit register. In this case, the current value in the SSTXD1 register can
be used by software to generate the next address or to determine if the last transaction
was a read or a write.
■
Using SSTXD1 and SSTXD0 as transmit registers for two peripheral devices: In
some systems, it may clarify the code and aid in debugging to view the two data transmit
registers as unique to different peripheral devices. This allows the last value transmitted
to each device to be examined by debug code.
14.5.5
Comparison to Other Devices
The SSI is mostly backward-compatible with software written for the Am186EM SSI.
Additional features have been added to the SSI implementation. In its default mode, the
SSI on the Am186CC/CH/CU microcontrollers is backward-compatible with the Am186EM
with the following exceptions:
■
The SSI status and configuration register locations in the address map are different.
SDEN
SCLK
Set
DE0
bit
Write
transmit
register
PB=0
DR/DT=0
PB=1
DR/DT=0
PB=1
PB=0
DR/DT=1
Read
receive
register
PB=1
PB=1
DR/DT=0
Read receive
PB=1
PB=0
DR/DT=1
PB=1
DR/DT=0
PB=0
DR/DT=1
Clear
DE0
bit
PB=0
DR/DT=0
SDATA
(dummy
read)
Read receive
register (returns
data from last
transaction to CPU
without generating
another SSI transfer)
register (returns
data from last
transaction to CPU
and generates another
SSI transfer)
MSB(Reverse shift order)LSB
Notes:
SDEN is configured to be active Low in the scenario shown above.
Any PIOs used as SSI enables should be inactive while SDEN is active.
The SSI data order is configured to be in Reverse mode (MSB first).
The SSI clock is configured to be in Normal mode.
Summary of Contents for Am186 CC
Page 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Page 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Page 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Page 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Page 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Page 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Page 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Page 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Page 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...