DMA Controller
Am186™CC/CH/CU Microcontrollers User’s Manual
8-13
4. If the GDxTC register is non-zero, it decrements.
5. If the GDxTC register became zero and either the Terminal Count (TC) bit is set or the
transfer type is unsynchronized, the Start/Stop (ST) bit is reset, and further DMA requests
on that channel are ignored.
6. If the GD
xTC register became zero and the Interrupt (INT) bit is set, an interrupt request
is generated. This action is independent of whether the TC bit is set.
An entire sequence of DMA cycles is initiated by setting the ST bit. This bit can be set
manually at any time, and is also set automatically by any write to the GDxTC register when
the Auto Start (AST) bit is set. Setting the ST bit initiates a sequence of DMA transactions
if one of the following is true:
■
The GDxTC register is non-zero.
■
The TC bit is 0 and the transfer type is source or destination synchronized.
If neither of these conditions are met, hardware resets the ST bit without executing any
DMA transfers. Otherwise, the ST bit is reset by the hardware after executing one or more
transfers as discussed in the previous DMA cycle description. If a transfer is synchronized
and the TC bit is 0, DMA transfers continue as long as DMA requests are being made until
the ST bit is manually cleared. This mode is typically used with the address wrap option to
implement circular buffers (see “Using Buffer Queues or Circular Buffers” on page 8-20).
8.5.6.3
General-Purpose DMA Transfer Suspension
The following conditions suspend general-purpose DMA transfers:
■
Deassertion of DRQ
■
A bus hold condition
■
A refresh cycle by an NMI/watchdog timer interrupt
■
A pending DMA request of equal or higher priority
■
The DHLT bit in the DMAHLT register set to 1 by an NMI or by software
8.5.6.4
General-Purpose DMA Source and Destination Addresses
Each general-purpose DMA channel has a 20-bit source address and a 20-bit destination
address. The 20-bit addresses are split over two source registers (GDxSRCL and
GDxSRCH) and two destination registers (GDxDSTL and GDxDSTH), with the four most
significant bits (AD19–AD16) going into a separate register from the 16 low-order bits
(AD15–AD0). The address is specified as a 20-bit linear address, not as a segment:offset
pair. For example, for the segment C000h and offset 1000h, the linear address would be:
(C000h x 16) + 1000h = C1000h; therefore, the low register = 1000h and the high
register = 0Ch. To use a DMA channel, software must initialize all four address registers
for that channel.
The addresses can be individually incremented or decremented after each transfer. For
more information, see “Incrementing or Decrementing Addresses” on page 8-15.
The source and destination addresses can each be in either memory space or I/O space.
This is specified by programming the SM/IO bit in the GDxCON1 register. The AD19–AD16
bits are ignored when the address is in I/O space. Because the DMA channels can perform
transfers to or from odd addresses, there is no restriction on values for the destination and
source address registers. Higher transfer rates can be achieved if all word transfers are
performed to and from even addresses so that accesses can occur in single 16-bit bus
Summary of Contents for Am186 CC
Page 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Page 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Page 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Page 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Page 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Page 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Page 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Page 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Page 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...