Altera UG-01080 Page 28 User Manual Download

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Figure 3-4: 10GBASE-R PHY IP Core In Arria V GZ Devices

Data

Wiring

PLD-PCS & Duplex PCS

PCS-PMA

PCS

TX PMA

PMA

RX PMA & CDR

Generic

PLL

Reset

Controller

Transceiver

Reconfiguration

Controller

PMA + Reset Control & Status

(Memory Map)

Tx Serial

Rx Serial

Control & Status

(Optional or by

I/F Specification)

Avalon-ST

Streaming

Data

Tx Data

Rx Data

Transceiver Protocol

Arria V GZ Transceiver Protocol

To/From

XCVR

Avalon-MM Slave

Avalon-MM Master

Avalon-MM

Management

Interface

to Embedded

Controller

3-4

10GBASE-R PHY IP Core

UG-01080

2015.01.19

Altera Corporation

10GBASE-R PHY IP Core

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Summary of Contents for UG-01080

Page 1: ...Altera Transceiver PHY IP Core User Guide Subscribe Send Feedback UG 01080 2015 01 12 101 Innovation Drive San Jose CA 95134 www altera com ...

Page 2: ...7 10GBASE R PHY Performance and Resource Utilization for Arria V GZ and Stratix V Devices 3 8 Parameterizing the 10GBASE R PHY 3 8 General Option Parameters 3 9 Analog Parameters for Stratix IV Devices 3 12 10GBASE R PHY Interfaces 3 13 10GBASE R PHY Data Interfaces 3 14 10GBASE R PHY Status 1588 and PLL Reference Clock Interfaces 3 17 Optional Reset Control and Status Interface 3 18 10GBASE R PHY...

Page 3: ...faces 4 22 10GBASE KR PHY Control and Status Interfaces 4 25 Daisy Chain Interface Signals 4 27 Embedded Processor Interface Signals 4 28 Dynamic Reconfiguration Interface Signals 4 29 Register Interface Signals 4 32 10GBASE KR PHY Register Definitions 4 32 PMA Registers 4 47 PCS Registers 4 48 Creating a 10GBASE KR Design 4 49 Editing a 10GBASE KR MIF File 4 50 Design Example 4 52 SDC Timing Cons...

Page 4: ...es 6 3 Parameterizing the XAUI PHY 6 3 XAUI PHY General Parameters 6 4 XAUI PHY Analog Parameters 6 6 XAUI PHY Analog Parameters for Arria II GX Cyclone IV GX HardCopy IV and Stratix IV Devices 6 6 Advanced Options Parameters 6 8 XAUI PHY Configurations 6 9 XAUI PHY Ports 6 10 XAUI PHY Data Interfaces 6 11 SDR XGMII TX Interface 6 12 SDR XGMII RX Interface 6 13 Transceiver Serial Data Interface 6 ...

Page 5: ...tion 8 3 Parameterizing the PHY IP Core for PCI Express PIPE 8 3 PHY for PCIe PIPE General Options Parameters 8 3 PHY for PCIe PIPE Interfaces 8 6 PHY for PCIe PIPE Input Data from the PHY MAC 8 7 PHY for PCIe PIPE Output Data to the PHY MAC 8 11 PHY for PCIe PIPE Clocks 8 13 PHY for PCIe PIPE Clock SDC Timing Constraints for Gen3 Designs 8 13 PHY for PCIe PIPE Optional Status Interface 8 14 PHY f...

Page 6: ...rameters 10 10 Low Latency PHY Analog Parameters 10 12 Low Latency PHY Interfaces 10 13 Low Latency PHY Data Interfaces 10 13 Optional Status Interface 10 15 Low Latency PHY Clock Interface 10 15 Optional Reset Control and Status Interface 10 16 Register Interface and Register Descriptions 10 17 Dynamic Reconfiguration 10 19 SDC Timing Constraints 10 20 Simulation Files and Example Testbench 10 21...

Page 7: ... Native PHY 12 4 PMA Parameters for Stratix V Native PHY 12 6 Standard PCS Parameters for the Native PHY 12 13 10G PCS Parameters for Stratix V Native PHY 12 29 Interfaces for Stratix V Native PHY 12 46 Common Interface Ports for Stratix V Native PHY 12 46 Standard PCS Interface Ports 12 53 10G PCS Interface 12 58 6 N Bonded Clocking 12 69 xN Non Bonded Clocking 12 73 SDC Timing Constraints of Str...

Page 8: ...face Ports 14 53 10G PCS Interface 14 58 SDC Timing Constraints of Arria V GZ Native PHY 14 70 Dynamic Reconfiguration for Arria V GZ Native PHY 14 71 Simulation Support 14 72 Cyclone V Transceiver Native PHY IP Core Overview 15 1 Cyclone Device Family Support 15 2 Cyclone V Native PHY Performance and Resource Utilization 15 2 Parameterizing the Cyclone V Native PHY 15 2 General Parameters 15 3 PM...

Page 9: ... Adaptive mode 16 22 Turning on Triggered DFE Mode 16 23 Setting the First Tap Value Using DFE in Manual Mode 16 23 Transceiver Reconfiguration Controller AEQ Registers 16 24 Transceiver Reconfiguration Controller ATX PLL Calibration Registers 16 26 Transceiver Reconfiguration Controller PLL Reconfiguration 16 28 Transceiver Reconfiguration Controller PLL Reconfiguration Registers 16 30 Transceive...

Page 10: ...4 Transceiver PHY Reset Controller Parameters 17 4 Transceiver PHY Reset Controller Interfaces 17 6 Timing Constraints for Bonded PCS and PMA Channels 17 10 Transceiver PLL IP Core for Stratix V Arria V and Arria V GZ Devices 18 1 Parameterizing the Transceiver PLL PHY 18 3 Transceiver PLL Parameters 18 3 Transceiver PLL Signals 18 4 Analog Parameters Set Using QSF Assignments 19 1 Making QSF Assi...

Page 11: ... PIPE Parameters in Stratix IV and Stratix V Devices 20 7 Differences Between PHY IP Core for PCIe PHY PIPE Ports for Stratix IV and Stratix V Devices 20 8 Differences Between Custom PHY Parameters for Stratix IV and Stratix V Devices 20 11 Differences Between Custom PHY Ports in Stratix IV and Stratix V Devices 20 13 Additional Information for the Transceiver PHY IP Core 21 1 Revision History for...

Page 12: ...face to access control and status registers and an Avalon Streaming Avalon ST interface to connect to the MAC for data transfer The following figure illustrates the top level modules that comprise the protocol specific transceiver PHY IP cores As illustrated the Altera Transceiver Reconfiguration Controller IP Core is instantiated separately 2015 Altera Corporation All rights reserved ALTERA ARRIA...

Page 13: ...erview 1G 10 Gbps Ethernet PHY IP Core on page 5 1 XAUI PHY IP Core on page 6 1 Interlaken PHY IP Core on page 7 1 PHY IP Core for PCI Express PIPE on page 8 1 Native Transceiver PHYs Each device family beginning with Series V devices offers a separate Native PHY IP core to provide low level access to the hardware There are separate IP Cores for Arria V Arria V GZ Cyclone V and Stratix V devices T...

Page 14: ... Serializer Deserializer Standard PCS optional 10G PCS optional As shown the Stratix V Native PHY connects to the separately instantiated Transceiver Reconfiguration Controller and Transceiver PHY Reset Controller Table 1 1 Native Transceiver PHY Datapaths Datapaths Stratix V Arria V Arria V GZ Cyclone V PMA Direct This datapath connects the FPGA fabric directly to the PMA minimizing latency You m...

Page 15: ...ratix V Devices on page 19 34 Non Protocol Specific Transceiver PHYs Non protocol specific transceiver PHYs provide more flexible settings than the protocol specific transceiver PHYs They include the Custom PHY Low Latency PHY and Deterministic Latency PHY IP Cores These PHYs include an Avalon Memory Mapped Avalon MM interface to access control and status registers and an Avalon Streaming Avalon S...

Page 16: ...lave components through a simple standard interface Refer to Transceiver PHY Top Level Modules Transceiver Reconfiguration Controller Altera Transceiver Reconfiguration Controller dynamically reconfigures analog settings in Arria V Cyclone V and Stratix V devices Reconfiguration allows you to compensate for variations due to process voltage and temperature PVT in 28 nm devices It is required for A...

Page 17: ...control in Stratix V devices refer to Transceiver Reset Control in Stratix V Devices in volume 3 of the Stratix V Device Handbook For Stratix IV devices refer to Reset Control and Power Down in volume 4 of the Stratix IV Device Handbook For Arria V devices refer to Transceiver Reset Control and Power Down in Arria V Devices For Cyclone V devices refer to Transceiver Reset Control and Power Down in...

Page 18: ...n files for Riviera PRO simulation tools instance_name _sim cadence Simulation files for Cadence simulation tools instance_name _sim mentor Simulation files for Mentor simulation tools The following table describes the key files and directories for the parameterized transceiver PHY IP core and the simulation environment which are in clear text Table 1 2 Transceiver PHY Files and Directories File N...

Page 19: ...ion files for Synopsys simulation tools The Verilog and VHDL transceiver PHY IP cores have been tested with the following simulators ModelSim SE Synopsys VCS MX Cadence NCSim If you select VHDL for your transceiver PHY only the wrapper generated by the Quartus II software is in VHDL All the underlying files are written in Verilog or System Verilog To enable simulation using a VHDL only ModelSim li...

Page 20: ...spd file Describes the list of compiled files and memory model hierarchy If your design includes multiple IP cores or Qsys systems that include spd files use this option for each file For example ip make simscript spd ip1 spd spd ip2 spd Require d output directory directory Directory path specifying the location of output files If unspecified the default setting is the directory from which ip make...

Page 21: ...ardware until you are satisfied with its functionality and performance Some IP cores require that you purchase a license for the IP core when you want to take your design to production After you purchase a license for an Altera IP core you can request a license file from the Altera Licensing page of the Altera website and install the license on your computer For additional information refer to Alt...

Page 22: ... Specify Parameters IP Complete Perform Functional Simulation Debug Design Does Simulation Give Expected Results Yes Optional Add Constraints and Compile Design The MegaWizard Plug In Manager flow offers the following advantages Allows you to parameterize an IP core variant and instantiate into an existing design For some IP cores this flow generates a complete example design and testbench 2 Alter...

Page 23: ...ncrypted RTL models and plain text RTL models These are all cycle accurate models The models allow for fast functional simulation of your IP core instance using industry standard VHDL or Verilog HDL simulators For some cores only the plain text RTL model is generated and you can simulate that model Note For more information about functional simulation models for Altera IP cores refer to Simulating...

Page 24: ...mple design for RTL simulation is located in the variation_name _example_design simulation directory Note For information about the Quartus II software including virtual pins refer to Quartus II Help Related Information Simulating Altera Designs Quartus II Help Simulate the IP Core This section describes how to simulate your IP core You can simulate your IP core variation with the functional simul...

Page 25: ... IV GT device To achieve higher bandwidths you can instantiate multiple channels The PCS is available in soft logic for Stratix IV GT devices it connects to a separately instantiated hard PMA The PCS connects to an Ethernet MAC via single data rate SDR XGMII running at 156 25 megabits per second Mbps and transmits data to a 10 Gbps transceiver PMA running at 10 3125 Gbps in a Stratix IV GT device ...

Page 26: ...es not require that all four channels in a quad run the 10GBASE R protocol Figure 3 2 Complete 10GBASE R PHY Design in Stratix IV GT Device To MAC To Embedded Controller Avalon MM connections 10GBASE R PHY Stratix IV Device SDR XGMII 72 bits 156 25 Mbps To MAC SDR XGMII 72 bits 156 25 Mbps Avalon MM PHY Management Bridge M S S Low Latency Controller S Transceiver Reconfig Controller Alt_PMA 10GBAS...

Page 27: ...Control Status Memory Map 10 GB BaseR CSR Tx Serial Rx Serial Reconfiguration Avalon MM Management Interface to Embedded Controller Control Status Conduits Optional or by I F Specification Avalon ST Streaming Data Tx Data Rx Data ArriaV GT 10GBASE RTop Level ArriaV GT 10GBASE R To From Transceiver S M S S UG 01080 2015 01 19 10GBASE R PHY IP Core 3 3 10GBASE R PHY IP Core Altera Corporation Send F...

Page 28: ...eset Control Status Memory Map Tx Serial Rx Serial S Control Status Optional or by I F Specification Avalon ST Streaming Data Tx Data Rx Data Transceiver Protocol ArriaV GZTransceiver Protocol To From XCVR Avalon MM Slave Avalon MM Master S M Avalon MM Management Interface to Embedded Controller 3 4 10GBASE R PHY IP Core UG 01080 2015 01 19 Altera Corporation 10GBASE R PHY IP Core Send Feedback ...

Page 29: ... table lists the latency through the PCS and PMA for Arria V GT devices with a 66 bit PMA The FPGA fabric to PCS interface is 64 bits wide The frequency of the parallel clock is 156 25 MHz which is line rate 10 3125 Gpbs interface width 64 Table 3 1 Latency for TX and RX PCS and PMA Arria V Devices PCS Parallel Clock Cycles PMA UI TX 28 131 RX 33 99 The following table lists the latency through th...

Page 30: ...g Codes 3 IP 10GBASERPCS primary IPR 10GBASERPCS renewal Product ID 00D7 Vendor ID 6AF7 10GBASE R PHY Device Family Support Device support for the IP core IP cores provide either final or preliminary support for target Altera device families These terms have the following definitions Final support Verified with final timing models for this device Preliminary support Verified with preliminary timin...

Page 31: ... software targeting a Stratix IV GT device The numbers of combinational ALUTs logic registers and memory bits are rounded to the nearest 100 Table 3 5 10GBASE R PHY Performance and Resource Utilization Stratix IV GT Device Channels Combinational ALUTs Logic Registers Bits Memory Bits 1 5200 4100 4700 4 15600 1300 18800 10 38100 32100 47500 10GBASE R PHY Performance and Resource Utilization for Arr...

Page 32: ...s this datapath Table 3 7 Latency PPM Difference Cycles 0 PPM 35 200 PPM 35 200 PPM 42 Note If latency is critical Altera recommends designing your own soft 10GBASE R PCS and connecting to the Low Latency PHY IP Core Parameterizing the 10GBASE R PHY The 10GBASE R PHY IP Core is available for the Arria V Arria V GZ Stratix IV or Stratix V device families Complete the following steps to configure th...

Page 33: ...ices only support duplex mode PLL type CMU ATX For Arria V GZ Stratix IV and Stratix V devices You can select either the CMU or ATX PLL The CMU PLL has a larger frequency range than the ATX PLL The ATX PLL is designed to improve jitter performance and achieves lower channel to channel skew Another advantage of the ATX PLL is that it does not use a transceiver channel while the CMU PLL does Altera ...

Page 34: ..._lock Enable rx_recovered_clk pin On Off When you turn this option On the RX recovered clock signal is an output signal Enable pll_locked status port On Off For Arria V and Stratix V devices When you turn this option On a PLL locked status signal is included as a top level signal of the core Use external PMA control and reconfig On Off For Stratix IV devices If you turn this option on the PMA cont...

Page 35: ... parameter if you are using external PMA and reconfiguration modules In Stratix V devices by default the logical channel 0 is assigned to either physical transceiver channel 1 or channel 4 of a transceiver bank However if you have already created a PCB with a different lane assignment for logical channel 0 you can use the work around shown in the example below Assignment of the starting channel nu...

Page 36: ...ter Transmitter VOD control setting 0 7 Sets VOD for the various TX buffers Pre emphasis pre tap setting 0 7 Sets the amount of pre emphasis on the TX buffer Invert the pre emphasis pre tap polarity setting On Off Determines whether or not the pre emphasis control signal for the pre tap is inverted If you turn this option on the pre emphasis control signal is inverted Pre emphasis first post tap s...

Page 37: ...lter Specifying a low value passes low frequencies Specifying a high value passes high frequencies Analog Parameters for Arria V Arria V GZ and Stratix V Devices Click on the appropriate links to review the analog parameters for these devices Related Information Analog Settings for Arria V Devices on page 19 2 Analog Settings for Arria V GZ Devices on page 19 11 Analog Settings for Stratix V Devic...

Page 38: ...l_powerdown tx_digitalreset n 1 0 tx_analogreset n 1 0 tx_cal_busy n 1 0 rx_digitalreset n 1 0 rx_analogreset n 1 0 rx_cal_busy n 1 0 Reset Control and Status Optional Note The block diagram shown in the GUI labels the external pins with the interface type and places the interface name inside the box The interface type and name are used in the Hardware Component Description File _hw tcl If you tur...

Page 39: ... soon as it comes out of reset xgmii_tx_clk Input The XGMII TX clock which runs at 156 25 MHz Connect xgmii_tx_clk to xgmii_rx_ clk to guarantee this clock is within 150 ppm of the transceiver reference clock XGMII RX Interface xgmii_rx_dc_ n 71 0 Output Contains 8 lanes of data and control for XGMII Each lane consists of 8 bits of data and 1 bit of control Lane 0 7 0 8 Lane 1 16 9 17 Lane 2 25 18...

Page 40: ...ive the RX datapath interface RX read FIFO Serial Interface rx_serial_data_ n Input Differential high speed serial input data using the PCML I O standard The clock is recovered from the serial data stream tx_serial_data_ n Output Differential high speed serial input data using the PCML I O standard The clock is embedded from the serial data stream Table 3 11 Mapping from XGMII TX Bus to XGMII SDR ...

Page 41: ...mii_rx_dc_ 25 18 xgmii_sdr_data 23 16 Lane 2 data xgmii_rx_dc_ 26 xgmii_sdr_ctrl 2 Lane 2 control xgmii_rx_dc_ 34 27 xgmii_sdr_data 31 24 Lane 3 data xgmii_rx_dc_ 35 xgmii_sdr_ctrl 3 Lane 3 control xgmii_rx_dc_ 43 36 xgmii_sdr_data 39 32 Lane 4 data xgmii_rx_dc_ 44 xgmii_sdr_ctrl 4 Lane 4 control xgmii_rx_dc_ 52 45 xgmii_sdr_data 47 40 Lane 5 data xgmii_rx_dc_ 53 xgmii_sdr_ctrl 5 Lane 5 control xg...

Page 42: ...he number of clock cycles tx_latency_adj_10g 15 0 Output When you enable 1588 this signal outputs real time latency in XGMII clock cycles 156 25 MHz for the TX PCS and PMA datapath for 10G mode Bits 0 to 9 represent the fractional number of clock cycles Bits 10 to 15 represent the number of clock cycles PLL Reference Clock pll_ref_clk Input For Stratix IV GT devices the TX PLL reference clock must...

Page 43: ... is also asserted if reconfiguration controller is reset It will not be asserted if you manually re trigger the calibration IP You must hold the channel in reset until calibration completes rx_digitalreset n 1 0 Input When asserted resets the RX PCS rx_analogreset n 1 0 Input When asserted resets the RX CDR rx_cal_busy n 1 0 Output When asserted indicates that the initial RX calibration is in prog...

Page 44: ...clk 156 25 MHz 161 1328 MHz 161 1328 MHz 10 3125 Gbps 10 3125 Gbps pll_ref_clk 644 53125 MHz 8 33 fPLL rx_coreclkin RX TX 10GBASE R PHY Clocks for Arria V GZ Devices The following figure illustrates clock generation and distribution for Arria V GZ devices 3 20 10GBASE R PHY Clocks for Arria V GZ Devices UG 01080 2015 01 19 Altera Corporation 10GBASE R PHY IP Core Send Feedback ...

Page 45: ... The phy_mgmt_clk_reset signal is the global reset that resets the entire PHY A positive edge on this signal triggers a reset Refer to the Reset Control and Power Down chapter in volume 2 of the Stratix IV Device Handbook for additional information about reset sequences in Stratix IV devices The PCS runs at 257 8125 MHz using the pma_rx_clock provided by the PMA You must provide the PMA an input r...

Page 46: ... bit control 64 bit data 8 bit control TX PMA 2 10 3125 Gbps serial RX PCS hard IP RX PCS soft IP 20 40 RX PMA 2 5 4 TX PLL 8 33 GPLL xgmii_rx_clk xgmii_tx_clk Related Information Reset Control and Power Down 10GBASE R PHY Clocks for Stratix V Devices The following figure illustrates clock generation and distribution in Stratix V devices 3 22 10GBASE R PHY Clocks for Stratix V Devices UG 01080 201...

Page 47: ..._clk clock inputs is 0 PPM The FIFO in the RX PCS can compensate 100 PPM between the RX PMA clock and xgmii_rx_clk You should use xgmii_rx_clk to drive xgmii_tx_clk The CDR logic recovers 257 8125 MHz clock from the incoming data 10GBASE R PHY Register Interface and Register Descriptions The Avalon MM PHY management interface provides access to the 10GBASER R PHY PCS and PMA registers You can use ...

Page 48: ...ite Input Write signal Asserted high phy_mgmt_read Input Read signal Asserted high phy_mgmt_waitrequest Output When asserted indicates that the Avalon MM slave interface is unable to respond to a read or write request When asserted control signals to the Avalon MM slave interface must remain constant Refer to the Typical Slave Read and Write Transfers and Master Transfers sections in the Avalon Me...

Page 49: ...1 31 0 RW reset_ch_bitmask Reset controller channel bitmask for digital resets The default value is all 1 s Channel n can be reset when bit n 1 Channel n cannot be reset when bit n 0 0x042 1 0 WO reset_control write Writing a 1 to bit 0 initiates a TX digital reset using the reset controller module The reset affects channels enabled in the reset_ch_bitmask Writing a 1 to bit 1 initiates a RX digit...

Page 50: ...tal Writing a 1 causes the RX digital reset signal to be asserted resetting the RX digital channels enabled in reset_ch_ bitmask You must write a 0 to clear the reset condition PMA Channel Control and Status 0x061 31 0 RW phy_serial_loopback Writing a 1 to channel n puts channel n in serial loopback mode For information about pre or post CDR serial loopback modes refer to Loopback Modes 0x064 31 0...

Page 51: ... asserted by the BER monitor block indicates that the PCS is recording a high BER From block BER monitor 2 R BLOCK_LOCK When asserted by the block synchronizer indicates that the PCS is locked to received blocks From Block Block synchronizer 3 R TX_FIFO_FULL When asserted indicates the TX FIFO is full From block TX FIFO 4 R RX_FIFO_FULL When asserted indicates the RX FIFO is full From block RX FIF...

Page 52: ... turning on Use external PMA control and reconfig available for Stratix IV GT devices Table 3 17 External PMA and Reconfiguration Signals Signal Name Direction Description gxb_pdn Input When asserted powers down the entire GT block Active high For Stratix IV de pll_pdn Input When asserted powers down the TX PLL Active high cal_blk_pdn Input When asserted powers down the calibration block Active hi...

Page 53: ...ation refer to Transceiver Reconfiguration Controller to PHY IP Connectivity on page 16 56 Allowing the Quartus II software to merge reconfi guration interfaces gives the Fitter more flexibility in placing transceiver channels Example 3 2 Informational Messages for the Transceiver Reconfiguration Interface Reconfiguration interface offset 0 is connected to the transceiver channel PHY IP will requi...

Page 54: ...the clocks in different time domains Be sure to verify the each clock domain is correctly buffered in the top level of your design You can find the sdc file in your top level working directory This is the same directory that includes your top level v or vhd file Example 3 3 Synopsys Design Constraints for Clocks Timing Information set_time_format unit ns decimal_places 3 Create Clocks create_clock...

Page 55: ..._clk xgmii_tx_clk set_false_path from siv_10gbaser_xcvr clk_reset_ctrl tx_pma_rstn to get_clocks siv_alt_pma pma_ch pma_direct receive_pcs clkout siv_alt_pma pma_ch pma_direct transmit_pcs clkout pll_siv_xgmii_clk altpll_component auto_generated pll1 clk 0 phy_mgmt_clk xgmii_tx_clk set_false_path from siv_10gbaser_xcvr clk_reset_ctrl tx_usr_rstn to get_clocks siv_alt_pma pma_ch pma_direct receive_...

Page 56: ...ion describes SDC examples and approaches to identify false timing paths About LogicLock Regions 10GBASE R PHY Simulation Files and Example Testbench Refer to Running a Simulation Testbench for a description of the directories and files that the Quartus II software creates automatically when you generate your 10GBASE R PHY IP Core Related Information Running a Simulation Testbench on page 1 6 3 32...

Page 57: ... ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconduct...

Page 58: ...plane Ethernet 10GBASE KR PHY IP Core includes the following new modules to enable operation over a backplane Link Training LT The LT mechanism allows the 10GBASE KR PHY to automatically configure the link partner TX PMDs for the lowest Bit Error Rate BER LT is defined in Clause 72 of IEEE Std 802 3ap 2007 Auto negotiation AN The Altera 10GBASE KR PHY IP Core can auto negotiate between 1000BASE KX...

Page 59: ... All speed grades except I4 and C4 Other device families No support Altera verifies that the current version of the Quartus II software compiles the previous version of each IP core Any exceptions to this verification are reported in the MegaCore IP Library Release Notes and Errata Altera does not verify compilation with IP core versions older than the previous release Note For speed grade informa...

Page 60: ...uto negotiation and link training 0 0 1 M20K 10GBASE KR PHY with FEC 3700 5100 40 M20K Parameterizing the 10GBASE KR PHY The10GBASE KR PHY IP Core is available for the Arria V GZ and Stratix V device families The IP variant allows you specify either the Backplane KR or 1Gb 10Gb Ethernet variant When you select the Backplane KR variant the Link Training LT and Auto Negotiation AN tabs appear The 1G...

Page 61: ...orithm Enable microprocessor interface On Off When you turn this option On the core includes a microprocessor interface which enables the microprocessor mode for link training Maximum bit error count 15 31 63 127 255 Specifies the maximum number of errors before the Link Training Error bit 0xD2 bit 4 is set indicating an unacceptable bit error rate You can use this parameter to tune PMA settings F...

Page 62: ... Value Set by the Preset command as defined in Clause 72 6 10 2 3 1 of the link training protocol This is the value from which the algorithm starts The default value is 60 PREPOSTVAL 0 31 Specifies the preset Pre tap Value The default value is 0 PREPREVAL 0 15 Specifies the preset Post tap value The default value is 0 INITMAINVAL 0 63 Specifies the Initial VOD Value Set by the Initialize command i...

Page 63: ...AN_SELECTOR Selector Field 0 31 IEEE selector S4 0 D4 0 of AN word Width of the Training Wait Counter 7 8 IEEE 802 3 clause 72 6 10 3 2 wait_timer_done should be between 100 and 300 frames 7 gives 127 frames 8 gives 255 frames 10GBASE R Parameters The 10GBASE R parameters specify basic features of the 10GBASE R PCS The FEC options allow you to specify the FEC ability Table 4 6 10GBASE R Parameters...

Page 64: ...Set FEC_ability bit on power up and reset On Off When you turn this option On the core sets the FEC ability bit on power up and reset Set FEC_Enable bit on power up and reset On Off When you turn this option On the core sets the FEC enable bit on power up and reset Set FEC_Error_Indication_ ability bit on power up and reset On Off When you turn this option On the core indicates errors to the PCS G...

Page 65: ...f you enable 1G mode Enable IEEE 1588 Precision Time Protocol On Off When you turn this option On the core includes a module in the PCS to implement the IEEE 1588 Precision Time Protocol PHY ID 32 bit 32 bit value An optional 32 bit value that serves as a unique identifier for a particular type of PCS The identifier includes the following components Bits 3 24 of the Organizationally Unique Identif...

Page 66: ...link_fail_ inhibit_time has expired before link_status is set to OK The legal range is 500 510 ms For more information refer to Clause 73 Auto Negotiation for Backplane Ethernet in IEEE Std 802 3ap 2007 Link fail inhibit time for 1Gb Ethernet 40 50 ms Specifies the time before link_status is set to FAIL or OK A link fails if the link_fail_inhibit_ time has expired before link_status is set to OK T...

Page 67: ...5 Ref Clk ATX CMU TX PLL For 10 GbE ATX CMU TX PLL For 1 GbE 1 25 Gb 10 3125 Gb Hard PMA Link Status S Reset Controller State Machine Arbiter Rate Change Requests AN LT Requests Transceiver Reconfig Controller 10 Gb Ethernet Hard PCS Cntl Status RX GMII Data TX GMII Data 125 MHz RX XGMII Data TX XGMII Data Shared Across Multiple Channels Can Share Across Multiple Channels 156 25 MHz 1 GIGE PCS 1G ...

Page 68: ...entified in this figure 1 The receiving link partner calculates the BER 2 The receiving link partner transmits an update to the transmitting link partner TX equalization parameters to optimize the TX equalization settings 3 The transmitting partner updates its TX equalization settings 4 The transmitting partner acknowledges the change This process is performed first for the VOD then the pre emphas...

Page 69: ...g link partner A 4 Transmit partner A updates its equalization settings 5 Transmit partner A acknowledges the change This procedure is repeated for the other two link partners Sequencer The Sequencer Rate change block controls the start up reset power on sequence of the PHY IP It automatically selects which PCS 1G 10GbE or Low Latency is required and sends requests to reconfigure the PCS The Seque...

Page 70: ...E KR Data mode After TX equalization completes this timing diagram shows the transition from Link Training mode to 10GBASE KR Data mode and MIF streaming Figure 4 6 Transition from Link Training to Data Mode pcs_mode_rc 5 0 lt_start_rc seq_start_rc MIF streaming rc_busy tap_to_upd 2 0 main_rc 5 0 post_rc 4 0 pre_rc 3 0 04 5 9 42 001 02 Related Information Changing Transceiver Settings Using Stream...

Page 71: ...guration 3 Initiate the MIF streaming process The state machine should also select the appropriate MIF stored in the ROMs to stream based on the requested mode 4 Wait for the reconfig_busy signal from the Transceiver Reconfiguration Controller to assert and then deassert indicating the reconfiguration process is complete 5 Toggle the digital resets for the reconfigured channel and wait for the lin...

Page 72: ...equests FEC Note If neither device requests FEC FEC is not enabled even if both devices have the FEC Ability The TX FEC encoder 2112 2080 creates 2112 bit FEC blocks or codewords from 32 64B 66B encoded and scrambled 10GBASE R words It compresses the 32 66 bit words into 32 65 bit words and generates 32 bit parity using the following polynomial g x x32 x23 x21 x11 x2 1 Parity is appended to the en...

Page 73: ...e of the received codeword The syndrome is the remainder from the polynomial division of the received codeword by g x If the syndrome is zero the codeword is correct If the syndrome is non zero you can use it to determine the most likely error Figure 4 9 Codewords Parity and Syndromes Data Parity Codeword Rem of Divide by g x Syndrome The Syndrome Is Also Equal to the Local Parity XOR Received Par...

Page 74: ... FEC decoder performs the 2112 2080 decoding by analyzing the received FEC block for errors It can correct burst errors of 11 bits per FEC block The FEC receive gearbox adapts the data width to the larger bus width of the PCS channel It supports a 64 65 ratio FEC Transcode Decoder The FEC transcode decoder performs 65 bit to 64B 66B reconstruction by regenerating the 64B 66B sync header 4 18 Forwa...

Page 75: ...ck_lock rxeq_done rx_hi_ber pll_locked rx_is_lockedtodata tx_cal_busy rx_cal_busy calc_clk_1g rx_data_ready rx_sync_status tx_pcfifo_error_1g rx_pcfifo_errog_1g lcl_rf tm_in_trigger 3 0 tm_out_trigger 3 0 rx_rlv rx_clkslip rx_latency_adj_1g 21 0 tx_latency_adj_1g 21 0 rx_latency_adj_10g 15 0 tx_latency_adj_10g 15 0 tx_frame rx_clr_counters rx_frame rx_block_lock rx_parity_good rx_parity_invalid rx...

Page 76: ...Transceiver PHY Reset Controller IP Core chapter in the Altera Transceiver PHY IP Core User Guide The following figure provides an overview of the clocking for this core Figure 4 11 Clocks for Standard and 10G PCS and TX PLLs xgmii_rx_clk 156 25 MHz xgmii_tx_clk 156 25 MHz 1G 10G PHY StratixV STD RX PCS StratixV TX PMA tx_coreclkin_1g 125 MHz StratixV RX PMA TX PLL TX PLL 40 rx_pld_clk rx_pma_clk ...

Page 77: ...0G mode Its frequency is 644 53125 or 322 265625 MHz pll_powerdown_1g Input Resets the 1Gb TX PLLs pll_powerdown_10g Input Resets the 10Gb TX PLLs tx_analogreset Input Resets the analog TX portion of the transceiver PHY tx_digitalreset Input Resets the digital TX portion of the transceiver PHY rx_analogreset Input Resets the analog RX portion of the transceiver PHY rx_digitalreset Input Resets the...

Page 78: ... Each lane consists of 8 bits of data and 1 bit of control xgmii_rx_clk Input Clock for SDR XGMII RX interface to the MAC The frequency is 156 25 MHz irrespective of 1588 being enabled or disabled Driven from the MAC This clock is derived from the transceiver reference clock pll_ref_clk_10g 10GBASE KR GMII Data Interface gmii_tx_d 7 0 Input TX data for 1G mode Synchronized to tx_clkout_ 1g clock T...

Page 79: ...rts this signal when Auto Negotiation completes 10GBASE KR PHY XGMII Mapping to Standard SDR XGMII Data The 72 bit TX XGMII data bus format is different than the standard SDR XGMII interface The following table lists the mapping of this non standard format to the standard SDR XGMII interface Table 4 12 TX XGMII Mapping to Standard SDR XGMII Interface Signal Name SDR XGMII Signal Name Description x...

Page 80: ...xgmii_sdr_ctrl 1 Lane 1 control xgmii_rx_dc 25 18 xgmii_sdr_data 23 16 Lane 2 data xgmii_rx_dc 26 xgmii_sdr_ctrl 2 Lane 2 control xgmii_rx_dc 34 27 xgmii_sdr_data 31 24 Lane 3 data xgmii_rx_dc 35 xgmii_sdr_ctrl 3 Lane 3 control xgmii_rx_dc 43 36 xgmii_sdr_data 39 32 Lane 4 data xgmii_rx_dc 44 xgmii_sdr_ctrl 4 Lane 4 control xgmii_rx_dc 52 45 xgmii_sdr_data 47 40 Lane 5 data xgmii_rx_dc 53 xgmii_sd...

Page 81: ...nually re trigger the calibration IP calc_clk_1g Input An independent clock to calculate the latency of the SGMII TX and RX FIFOs It is only required for when you enable 1588 in 1G mode The calc_clk_1g should have a frequency that is not equivalent to 8 ns 125MHz The accuracy of the PCS latency measurement is limited by the greatest common denominator GCD of the RX and TX clock periods 8 ns and ca...

Page 82: ... can be used for hardware testing by using an oscilloscope or logic analyzer to trigger events You can ignore this signal if not used rx_rlv Output When asserted indicates a run length violation rx_clkslip Input When you turn this signal on the deserializer skips one serial bit or the serial clock is paused for one cycle to achieve word alignment As a result the period of the parallel clock can be...

Page 83: ...nchronous status flag output of the RX FEC module When asserted indicates the beginning of a 2112 bit received FEC frame rx_block_lock Output Asynchronous status flag output of the RX FEC module When asserted indicates successful FEC block lock rx_parity_good Output Asynchronous status flag output of the RX FEC module When asserted indicates that the parity calculation is good for the current rece...

Page 84: ...dicates that the state machine has locked to the training frames dmo_rmt_rx_ready Output Corresponds to the link partner s remote receiver ready bit dmo_lcl_coefl 5 0 Output Local update low bits 5 0 In daisy chained configurations the local update coefficients substitute for the coefficients that would be set using Link Training dmo_lcl_coefh 1 0 Output Local update high bits 13 12 In daisy chain...

Page 85: ...ved training frame lock upo_cm_done Output When asserted indicates the master state machine handshake is complete upo_bert_done Output When asserted indicates the BER timer is at its maximum count upo_ber_cnt w 1 0 Output Records the BER count upo_ber_max Output When asserted the BER counter has rolled over upo_coef_max Output When asserted indicates that the remote coefficients are at their maxim...

Page 86: ...n tap value This signal translates to the first post tap settings The following example mappings are defined 5 b11111 FIR_1PT_6P2MA 5 b11110 FIR_1PT_6P0MA 5 b00001 FIR_1PT_P2MA 5 b00000 FIR_1PT_DISABLED pre_rc 3 0 Output The pre cursor TX equalization tap value This signal translates to pre tap settings The following example mappings are defined 4 b1111 FIR_PRE_3P0MA 4 b1110 FIR_PRE_P28MA 4 b0001 ...

Page 87: ...ode 1 0 Output Specifies CTLE mode These signals are valid at the rising edge of the ctle_start_rc signal and held until the falling edge of the rc_busy signal The following encodings are defined 2 b00 ctle_rc 3 0 drives the value of CTLE set during link training 2 b01 Reserved 2b 10 Reserved 2 b11 Reserved ctle_rc 3 0 Output RX CTLE value This signal is valid at the rising edge of the ctle_start_...

Page 88: ...mgmt_clk_reset Input Resets the PHY management interface This signal is active high and level sensitive mgmt_addr 7 0 Input 8 bit Avalon MM address mgmt_writedata 31 0 Input Input data mgmt_readdata 31 0 Output Output data mgmt_write Input Write signal Active high mgmt_read Input Read signal Active high mgmt_waitrequest Output When asserted indicates that the Avalon MM slave interface is unable to...

Page 89: ...s timer set Disable AN Timer 0 2 RW Disable LF Timer When set to 1 disables the Link Fault timer When set to 0 the Link Fault timer is enabled 6 4 RW SEQ Force Mode 2 0 Forces the sequencer to a specific protocol Must write the Reset SEQ bit to 1 for the Force to take effect The following encodings are defined 3 b000 No force 3 b001 GigE 3 b010 Reserved 3 b011 Reserved 3 b100 10GBASE R 3 b101 10GB...

Page 90: ...EE 802 3ap 2007 17 R Enable KR FEC Error Indication Ability When set to 1 indicates that the 10GBASE KR PHY is capable of reporting FEC decoding errors to the PCS For more information refer to the KR FEC variable FEC_enable_ Error_to_PCS and 10GBASE KR PMD control register bit 1 171 1 as defined in Clause 74 8 3 of IEEE 302 3ap 2007 0xB2 0 RW FEC TX trans error When asserted indicates that the err...

Page 91: ...et to 0 operates normally 5 RW Override AN When set to 1 the override settings defined by the AN_TECH AN_FEC and AN_PAUSE registers take effect 0xC1 0 RW Reset AN When set to 1 resets all the 10GBASE KR Auto Negotiation state machines This bit is self clearing 4 RW Restart AN TX SM When set to 1 restarts the 10GBASE KR TX state machine This bit self clears This bit is active only when the TX state...

Page 92: ...7 1 2 of Clause 45 of IEEE 802 3ap 2007 7 RO LP AN Ability When set to 1 the link partner is able to perform Auto Negotiation When 0 the link partner is not able to perform Auto Negotiation For more information refer to bit 7 1 0 of Clause 45 of IEEE 802 3ap 2007 8 RO Enable FEC When asserted indicates that auto negotiation is complete and that communicate includes FEC For more information refer t...

Page 93: ...N_ FEC 0 Capability 25 AN_ FEC 1 Request You must write 0xC0 5 to 1 b1 for these overrides to take effect 30 28 RW Override AN_ PAUSE 2 0 Specifies an AN_PAUSE value to override The following encodings are defined 28 AN_PAUSE 0 Pause Ability 29 AN_PAUSE 1 Asymmetric Direction 30 AN_PAUSE 2 Reserved Need to set 0xC0 bit 5 to take effect 0xC4 31 0 RW User base page high The Auto Negotiation TX state...

Page 94: ...ined 4 0 Selector 9 5 Echoed Nonce which are set by the state machine 12 10 Pause bits 12 ACK2 bit 13 RF bit 14 ACK controlled by the state machine 15 Next page bit 0xC8 31 0 RO LP base page high The AN RX state machine received these bits from the link partner The following bits are defined 31 30 Reserved 29 5 Correspond to page bits 45 21 which are the technology ability 4 0 Correspond to bits 2...

Page 95: ...0 28 RO AN LP ADV Pause Ability_C 2 0 Received pause ability bits Pause C0 C1 is encoded in bits D11 D10 of the base link codeword in Clause 73 AN as follows C0 is the same as PAUSE as defined in Annex 28B C1 is the same as ASM_DIR as defined in Annex 28B C2 is reserved For more information refer to bits AN LP base page ability registers 7 19 7 21 of Clause 45 of IEEE 802 3ap 2007 0xD0 0 RW Link T...

Page 96: ...ailure bit 0xD2 3 Used during UNH IOL testing When set to 0 initializes the PMA values upon entry into Training_Failure state 16 RW Ovride LP Coef enable When set to 1 overrides the link partner s equalization coefficients software changes the update commands sent to the link partner TX equalizer coefficients When set to 0 uses the Link Training logic to determine the link partner coefficients Use...

Page 97: ...m for all values Link training settles on the max_post_step for the posttap value 31 29 RW max_post_step Number of TX posttap steps from the initialization state when in max_mode 0xD1 0 RW Restart Link training When set to 1 resets the 10GBASE KR start up protocol When set to 0 continues normal operation This bit self clears For more information refer to the state variable mr_ restart_training as ...

Page 98: ...For more information refer to the state variable training_failure as defined in Clause 72 6 10 3 1 and bit 10GBASE_KR PMD status register bit 1 151 3 of IEEE 802 3ap 2007 4 RO Link Training Error When set to 1 excessive errors occurred during Link Training When set to 0 the BER is acceptable 5 RO Link Training Frame lock Error When set to 1 indicates a frame lock was lost during Link Training If t...

Page 99: ... you override training by setting the Ovride Coef enable control bit these bits become writeable The following fields are defined 5 4 Coefficient 1 update 2 b11 Reserved 2 b01 Increment 2 b10 Decrement 2 b00 Hold 3 2 Coefficient 0 update same encoding as 5 4 1 0 Coefficient 1 update same encoding as 5 4 For more information refer to bit 10G BASE KR LD coefficient update register bits 1 154 5 0 in ...

Page 100: ...RO or RW LP coefficient update 5 0 Reflects the contents of the first 16 bit word of the training frame most recently received from the control channel Normally the bits in this register are read only however when training is disabled by setting low the KR Training enable control bit these bits become writeable The following fields are defined 5 4 Coefficient 1 update 2 b11 Reserved 2 b01 Incremen...

Page 101: ...channel The following fields are defined 5 4 Coefficient 1 2 b11 Maximum 2 b01 Minimum 2 b10 Updated 2 b00 Not updated 3 2 Coefficient 0 same encoding as 5 4 n 1 0 Coefficient 1 same encoding as 5 4 For more information refer to bit 10G BASE KR LP status report register bits 1 153 5 0 in Clause 45 2 1 79 of IEEE 802 3ap 2007 30 RO LP Receiver ready When set to 1 the link partner receiver has deter...

Page 102: ...ing RX Equalization 0xD6 5 0 RW LT VODMAX ovrd Override value for the VMAXRULE parameter When enabled this value substitutes for the VMAXRULE to allow channel by channel override of the device settings This only effects the local device TX output for the channel specified This value must be greater than the INITMAINVAL parameter for proper operation Note this will also override the PREMAINVAL para...

Page 103: ...e override value for the VPRERULE parameter stored in the LT VPre ovrd register field PMA Registers The PMA registers allow you to reset the PMA and provide status information Table 4 20 PMA Registers Reset and Status The following PMA registers allow you to reset the PMA and provide status information Addr Bit Access Name Description 0x22 0 RO pma_tx_pll_is_ locked Indicates that the TX PLL is lo...

Page 104: ...rted RX data is input to the 8B 10B decoder 2 RW rx_bitreversal_enable When set to 1 enables bit reversal on the RX interface The RX data is input to the word aligner 3 RW rx_bytereversal_ enable When set enables byte reversal on the RX interface The RX data is input to the byte deserializer 4 RW force_electrical_idle When set to 1 forces the TX outputs to electrical idle 0xA9 0 R rx_syncstatus Wh...

Page 105: ...ta Creating a 10GBASE KR Design Here are the steps you must take to create a 10GBASE KR design using this PHY 1 Generate the 10GBASE KR PHY with the required parameterization 2 Generate a Transceiver Reconfiguration Controller with the correct number of reconfiguration interfaces based on the number of channels you are using This controller is connected to all the transceiver channels It implement...

Page 106: ...GBASE KR MIF file to change between 1G and 10Gb Ethernet The MIF format contains all bit settings for the transceiver PMA and PCS Because the 10GBASE KR PHY IP Core only requires PCS reconfiguration for a rate change the PMA settings should not change Removing the PMA settings from the MIF file also prevents an unintended overwrite of PMA parameters set through other assignments A few simple edits...

Page 107: ...mple 4 1 Edits to a MIF to Remove PMA Settings UG 01080 2015 01 19 Editing a 10GBASE KR MIF File 4 51 Backplane Ethernet 10GBASE KR PHY IP Core with Early Access FEC Option Altera Corporation Send Feedback ...

Page 108: ...CSR Avalon MM Slave Native Hard PHY STD RX PCS TX PMA RX PMA STD TX PCS 10 GB TX PCS 10 GB RX PCS Divide GMII RS Auto Neg cls 73 Link Training cls 72 KR PHY IP Sequencer NF Reconfiguration Registers CSR Avalon MM Slave XGMII CLK FPLL 1G Ref CLK CMU PLL 10G Ref CLK ATX PLL Reset Control Reset Control Reset Control Reset Control CH0 PHY_ADDR 0x0 CH1 PHY_ADDR 0x1 CH2 PHY_ADDR 0x2 CH3 PHY_ADDR 0x3 NF_...

Page 109: ...erential Manchester Encoding FEC Forward error correction GMII Gigabit Media Independent Interface KR Short hand notation for Backplane Ethernet with 64b 66b encoding LD Local Device LT Link training in backplane Ethernet Clause 72 for 10GBASE KR and 40GBASE KR4 LP Link partner to which the LD is connected MAC Media Access Control MII Media independent interface OSI Open System Interconnection PCS...

Page 110: ...S receives and transmits XGMII data The Standard PCS receives and transmits GMII data An Avalon Memory Mapped Avalon MM slave interface provides access to PCS registers the PMA receives and transmits serial data 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U...

Page 111: ...gement Interface PCS Reconfig Request Optional 1588TX and RX Latency Adjust 1G and 10G To From 1G 10Gb Ethernet MAC RX GMII Data TX GMII Data 125 MHz RX XGMII Data TX XGMII Data 156 25 MHz 1 GIGE PCS An Avalon Memory Mapped Avalon MM slave interface provides access to the 1G 10GbE PHY IP Core registers These registers control many of the functions of the other blocks Many of these bits are defined...

Page 112: ...he previous release Note For speed grade information refer to DC and Switching Characteristics for Stratix V Devices in the Stratix V Device Datasheet Related Information Stratix V Device Datasheet 1G 10 GbE PHY Performance and Resource Utilization This topic provides performance and resource utilization for the IP core in Arria V GZ and Stratix V devices The following table shows the typical expe...

Page 113: ...elect 1G10GbE and 10GBASE KR PHY 3 Use the tabs on the MegaWizard Plug In Manager to select the options required for the protocol 4 Refer to the topics listed as Related Links to understand and specify 1G 10GbE parameters 5 Click Finish to generate your parameterized 1G 10GbE PHY IP Core Related Information Speed Detection Parameters on page 4 10 PHY Analog Parameters on page 4 10 1G 10GbE PHY Int...

Page 114: ...default is 125 MHz Related Information 1588 Delay Requirements on page 3 30 Speed Detection Parameters Selecting the speed detection option gives the PHY the ability to detect to link partners that support 1G 10GbE but have disabled Auto Negotiation During Auto Negotiation if AN cannot detect Differential Manchester Encoding DME pages from a link partner the Sequencer reconfigures to 1GE and 10GE ...

Page 115: ... for 1Gb Ethernet 40 50 ms Specifies the time before link_status is set to FAIL or OK A link fails if the link_fail_inhibit_ time has expired before link_status is set to OK The legal range is 40 50 ms PHY Analog Parameters You can specify analog parameters using the Quartus II Assignment Editor the Pin Planner or the Quartus II Settings File qsf Related Information Analog Settings for Arria V GZ ...

Page 116: ... rx_cal_busy calc_clk_1g rx_syncstatus tx_pcfifo_error_1g rx_pcfifo_error_1g lcl_rf tm_in_trigger 3 0 tm_out_trigger 3 0 rx_rlv rx_clkslip rx_latency_adj_1g 21 0 tx_latency_adj_1g 21 0 rx_latency_adj_10g 15 0 tx_latency_adj_10g 15 0 rx_data_ready Transceiver Serial Data XGMII and GMII Interfaces Avalon MM PHY Management Interface Clocks and Reset Interface Status The block diagram shown in the GUI...

Page 117: ...ansceiver PHY Reset Controller IP Core which is a separately instantiated module not included in the 1G 10GbE and 10GBASE KR variants The Transceiver PHY Reset Controller IP Core resets the TX PLL and RX analog circuits and the TX and RX digital circuits When complete the Reset Controller asserts the tx_ready and rx_ready signals The following figure provides an overview of the clocking for this I...

Page 118: ...e 1G mode Its frequency is 125 or 62 5 MHz pll_ref_clk_10g Input Reference clock for the PMA block in 10G mode Its frequency is 644 53125 or 322 265625 MHz pll_powerdown_1g Input Resets the 1Gb TX PLLs pll_powerdown_10g Input Resets the 10Gb TX PLLs tx_analogreset Input Resets the analog TX portion of the transceiver PHY tx_digitalreset Input Resets the digital TX portion of the transceiver PHY rx...

Page 119: ...ta for 1G mode Synchronized to tx_clkout_ 1g clock The RX PCS 8B 10B decoders decodes this data and sends it to the MAC gmii_tx_en Input When asserted indicates the start of a new frame It should remain asserted until the last byte of data on the frame is present on gmii_tx_d gmii_tx_err Input When asserted indicates an error May be asserted at any time during a frame transfer to indicate an error...

Page 120: ...ignal Name Description xgmii_tx_dc 7 0 xgmii_sdr_data 7 0 Lane 0 data xgmii_tx_dc 8 xgmii_sdr_ctrl 0 Lane 0 control xgmii_tx_dc 16 9 xgmii_sdr_data 15 8 Lane 1 data xgmii_tx_dc 17 xgmii_sdr_ctrl 1 Lane 1 control xgmii_tx_dc 25 18 xgmii_sdr_data 23 16 Lane 2 data xgmii_tx_dc 26 xgmii_sdr_ctrl 2 Lane 2 control xgmii_tx_dc 34 27 xgmii_sdr_data 31 24 Lane 3 data xgmii_tx_dc 35 xgmii_sdr_ctrl 3 Lane 3 ...

Page 121: ...ta xgmii_rx_dc 44 xgmii_sdr_ctrl 4 Lane 4 control xgmii_rx_dc 52 45 xgmii_sdr_data 47 40 Lane 5 data xgmii_rx_dc 53 xgmii_sdr_ctrl 5 Lane 5 control xgmii_rx_dc 61 54 xgmii_sdr_data 55 48 Lane 6 data xgmii_rx_dc 62 xgmii_sdr_ctrl 6 Lane 6 control xgmii_rx_dc 70 63 xgmii_sdr_data 63 56 Lane 7 data xgmii_rx_dc 71 xgmii_sdr_ctrl 7 Lane 7 control Serial Data Interface Table 5 10 Serial Data Signals Sig...

Page 122: ...ent pattern tx_pcfifo_error_1g Output When asserted indicates that the Standard PCS TX phase compensation FIFO is full rx_pcfifo_error_1g Output When asserted indicates that the Standard PCS RX phase compensation FIFO is full lcl_rf Input When asserted indicates a Remote Fault RF The MAC sends this fault signal to its link partner Bit D13 of the Auto Negotiation Advanced Remote Fault register 0xC2...

Page 123: ...ts 0 to 9 represent fractional number of clock cycles Bits 10 to 15 represent number of clock cycles rx_data_ready Output When asserted indicates that the MAC can begin sending data to the 10GBASE KRPHY IP Core Register Interface Signals The Avalon MM master interface signals provide access to all registers Refer to the Typical Slave Read and Write Transfers and Master Transfers sections in the Av...

Page 124: ...cts To avoid any unspecified bits to be erroneously overwritten you must perform read modify writes to change the register values Table 5 13 1G 10GbE Register Definitions Addr Bit R W Name Description 0xB0 0 RW Reset SEQ When set to 1 resets the sequencer This bit must be used in conjunction with SEQ Force Mode 2 0 This reset self clears 1 Reserved 2 RW Disable LF Timer When set to 1 disables the ...

Page 125: ...ternal RX analog reset signal to be asserted You must write a 0 to clear the reset condition 3 RW reset_rx_ digital Writing a 1 causes the internal RX digital reset signal to be asserted You must write a 0 to clear the reset condition 0x61 31 0 RW phy_serial_ loopback Writing a 1 puts the channel in serial loopback mode 0x64 31 0 RW pma_rx_set_ locktodata When set programs the RX CDR PLL to lock t...

Page 126: ...etect When set to 1 indicates the 1G word aligner has detected a comma 2 R rx_rlv When set to 1 indicates a run length violation 3 R rx_rmfifodatainserted When set to 1 indicates the rate match FIFO inserted code group 4 R rx_rmfifodatadeleted When set to 1 indicates that rate match FIFO deleted code group 5 R rx_disperr When set to 1 indicates an RX 8B 10B disparity error 6 R rx_errdetect When se...

Page 127: ...egotia tion sequence For normal operation set this bit to 0 which is the default value This bit is self clearing 12 RW AUTO_ NEGOTIATION_ ENABLE Set this bit to 1 to enable Clause 37 Auto Negotiation The default value is 1 15 RW Reset Set this bit to 1 to generate a synchronous reset pulse which resets all the PCS state machines comma detection function and the 8B 10B encoder and decoder For norma...

Page 128: ...metric pause 2 b11 Pause is supported on TX and RX 13 12 RW RF2 RF1 Remote fault condition for local device The following encodings are defined for RF1 RF2 2 b00 No error link is valid reset condition 2 b0 1 Offline 2 b10 Failure condition 2 b11 Auto negotiation error 14 RO ACK Acknowledge for local device A value of 1 indicates that the device has received three consecutive matching ability value...

Page 129: ...ition 2 b11 Auto negotiation error 14 R ACK Acknowledge for link partner A value of 1 indicates that the device has received three consecutive matching ability values from its link partner 15 R NP Next page In link partner register When set to 0 the link partner has a Next Page to send When set to 1 the link partner does not a Next Page Next Page is not supported in Auto Negotiation 0x96 0 R LINK_...

Page 130: ...eted code group 5 R rx_disperr When set to 1 indicates an RX 8B 10B disparity error 6 R rx_errdetect When set to 1 indicates an RX 8B 10B error detected 1G 10GbE Dynamic Reconfiguration from 1G to 10GbE This topic illustrates the necessary logic to reconfigure between the 1G and 10G data rates The following figure illustrates the necessary modules to create a design that can dynamically change bet...

Page 131: ...ard PCS Cntl Status RX GMII Data TX GMII Data 125 MHz RX XGMII Data TX XGMII Data Shared Across Multiple Channels Can Share Across Multiple Channels 156 25 MHz 1 GIGE PCS 1G 10Gb Ethernet MAC 1G 10Gb Ethernet MAC 1G 10G 1 Gb Ethernet Standard Hard PCS 1G 10GbE PHY Arbitration Logic Requirements This topic describes the arbitration functionality that you must implement The arbiter should implement ...

Page 132: ...to assert and then deassert indicating the reconfiguration process is complete 5 Toggle the digital resets for the reconfigured channel and wait for the link to be ready 6 Deassert the ack busy signal for the selected channel Deassertion of ack busy indicates to the arbiter that the reconfiguration process is complete and the system is ready to service another request Editing a 1G 10GbE MIF File T...

Page 133: ...channel being serviced causing the requestor to deassert its request signal 5 Create a state machine that controls the reconfiguration process The state machine should a Receive the prioritized reconfiguration request from the arbiter b Put the Transceiver Reconfiguration Controller into MIF streaming mode c Select the correct MIF and stream it into the appropriate channel d Wait for the reconfigu...

Page 134: ...onfiguration interfaces rc_busy Input When asserted indicates that reconfiguration is in progress lt_start_rc Output When asserted starts the TX PMA equalization reconfiguration main_rc 5 0 Output The main TX equalization tap value which is the same as VOD The following example mappings to the VOD settings are defined 6 b111111 FIR_MAIN_12P6MA 6 b111110 FIR_MAIN_12P4MA 6 b000001 FIR_MAIN_P2MA 6 b0...

Page 135: ...signal and held until the falling edge of the rc_busy signal The following encodings are defined 2 b00 Disable DFE 2 b01 DFE triggered mode 2 b10 Reserved def_start_rcd b11 Reserved ctle_start_rc Output When asserted starts continuous time linear equalization CTLE reconfiguration ctle_mode 1 0 Output Specifies CTLE mode These signals are valid at the rising edge of the ctle_start_rc signal and hel...

Page 136: ...EE 802 3 2005 Standard standard The 10G PCS implements the 10 Gb Ethernet protocol as defined in IEEE 802 3 2005 Standard You can switch dynamically between the 1G and 10G PCS using the Altera Transceiver Reconfiguration Controller IP Core to reprogram the core This Ethernet core targets 1G 10GbE applications including network interfaces to 1G 10GbE dual speed SFP pluggable modules 1G 10GbE 10GBAS...

Page 137: ... 1 Gb Ethernet Standard Hard PCS Optional To From Modules in the PHY MegaCore Control and Status Registers Avalon MM PHY Management Interface PCS Reconfig Request Optional 1588TX and RX Latency Adjust 1G and 10G To From 1G 10Gb Ethernet MAC RX GMII Data TX GMII Data 125 MHz RX XGMII Data TX XGMII Data 156 25 MHz 1 GIGE PCS An Avalon Memory Mapped Avalon MM slave interface provides access to the 1G...

Page 138: ...guration Registers CSR Avalon MM Slave Native Hard PHY STD RX PCS TX PMA RX PMA STD TX PCS 10 GB TX PCS 10 GB RX PCS Divide GMII RS Auto Neg cls 73 Link Training cls 72 KR PHY IP Sequencer NF Reconfiguration Registers CSR Avalon MM Slave XGMII CLK FPLL 1G Ref CLK CMU PLL 10G Ref CLK ATX PLL Reset Control Reset Control Reset Control Reset Control CH0 PHY_ADDR 0x0 CH1 PHY_ADDR 0x1 CH2 PHY_ADDR 0x2 C...

Page 139: ...ronyms This table defines some commonly used Ethernet acronyms Table 5 18 Ethernet Acronyms Acronym Definition AN Auto Negotiation in Ethernet as described in Clause 73 of IEEE 802 3ap 2007 BER Bit Error Rate DME Differential Manchester Encoding FEC Forward error correction GMII Gigabit Media Independent Interface KR Short hand notation for Backplane Ethernet with 64b 66b encoding LD Local Device ...

Page 140: ...ment PMD Physical Medium Dependent SGMII Serial Gigabit Media Independent Interface WAN Wide Area Network XAUI 10 Gigabit Attachment Unit Interface UG 01080 2015 01 19 Acronyms 5 31 1G 10 Gbps Ethernet PHY IP Core Altera Corporation Send Feedback ...

Page 141: ...iled information about the XAUI transceiver channel datapath clocking and channel placement refer to the XAUI section in the Transceiver Configurations in Stratix V Devices chapter of the Stratix V Device Handbook Related Information IEEE 802 3 Clause 48 Transceiver Configurations in Stratix V Devices 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUART...

Page 142: ...al support Verified with final timing models for this device Preliminary support Verified with preliminary timing models for this device Table 6 2 Device Family Support Device Family Support XAUI Arria II GX Hard PCS and PMA Final Arria II GZ Hard PCS and PMA Final Arria V GX Soft PCS PMA Final Arria V SoC Soft PCS PMA Final Arria V GZ devices Soft PCS PMA Final Cyclone IV GX Hard PCS and PMA Fina...

Page 143: ...mbinational ALUTS Dedicated Logic Registers Memory Bits Soft XAUI 4 4500 3200 5100 Hard XAUI 4 2000 13000 0 XAUI PHY Performance and Resource Utilization for Arria V GZ and Stratix V Devices This section describes performance and resource utilization for Arria V GZ and Stratix V Devices For the Arria V GZ 5AGZME5K2F40C3 device the XAUI PHY uses 1 of ALMs and less than 1 of M20K memory primary and ...

Page 144: ...s XAUI PHY In Arria II GX Cyclone IV GX HardCopy IV and Stratix IV devices this starting channel number must be 0 or a multiple of 4 In Arria V GZ and Stratix V devices logical lane 0 should be assigned to either physical transceiver channel 1 or channel 4 of a transceiver bank However if you have already created a PCB with a different lane assignment for logical lane 0 you can use the workaound s...

Page 145: ...LL is designed to improve jitter performance and achieves lower channel to channel skew however it supports a narrower range of data rates and reference clock frequencies Another advantage of the ATX PLL is that it does not use a transceiver channel while the CMU PLL does This parameter is available for the soft PCS and DDR XAUI The ATX PLL is not available for all devices Base data rate 1 Lane ra...

Page 146: ...log Parameters This section describes the analog parameters for the IP core Click on the appropriate link to specify the analog options for your device XAUI PHY Analog Parameters for Arria II GX Cyclone IV GX HardCopy IV and Stratix IV Devices on page 6 6 Related Information Analog Settings for Arria V Devices on page 19 2 Analog Settings for Arria V GZ Devices on page 19 11 Analog Settings for Cy...

Page 147: ...ces Invert the pre emphasis second post tap polarity On Off Determines whether or not the pre emphasis control signal for the second post tap is inverted If you turn this option on the pre emphasis control signa is inverted Available for HardCopy IV and Stratix IV devices Receiver common mode voltage Tri state 0 82V 1 1v Specifies the RX common mode voltage Receiver termination resistanc OCT_85_OH...

Page 148: ... control and configu ration On Off If you turn this option on the PMA signals are brought up to the top level of the XAUI IP Core This option is useful if your design includes multiple instantiations of the XAUI PHY IP Core To save FPGA resources you can instantiate the Low Latency PHY Controller and Transceiver Reconfiguration Controller IP Cores separately in your design to avoid having these IP...

Page 149: ...ore for more information about this IP core The Transceiver Reconfiguration Controller is always separately instantiated in Stratix V and Arria V GZ devices Figure 6 2 XAUI PHY with Internal Transceiver Reconfiguration Control System Interconnect Fabric Inter leave PCS S Alt_PMA S S Low Latency Controller S Transceiver Reconfiguration Controller Transceiver Channel Hard XAUI PHY 4 x 3 125 Gbps ser...

Page 150: ...II Handbook Figure 6 3 XAUI Top Level Signals Hard IP PCS and PMA xgmii_tx_dc 71 0 xgmii_tx_clk xgmii_rx_dc 71 0 xgmii_rx_clk phy_mgmt_clk phy_mgmt_clk_reset phy_mgmt_address 8 0 phy_mgmt_writedata 31 0 phy_mgmt_readdata 31 0 phy_mgmt_write phy_mgmt_read phy_mgmt_waitrequest pll_ref_clk rx_analogreset rx_digitalreset tx_digitalreset XAUI Top Level Signals Hard IP Implementation PMA Channel Control...

Page 151: ...col The interface does not include ready or valid signals consequently the sources always drive data and the sinks must always be ready to receive data For more information about the Avalon ST protocol including timing diagrams refer to the Avalon Interface Specifications Depending on the parameters you choose the application interface runs at either 156 25 Mbps or 312 5 Mbps At either frequency d...

Page 152: ...amble Figure 6 7 Byte 5 Start of Frame Transmission Example tx_clk txc 7 0 txd 7 0 txd 23 8 txd 31 24 txd 39 32 txd 55 40 txd 63 56 FF 1F 00 F8 FF 07 AA frame data 0707 AAAA AAAA AA frame data 07 sfd AB frame data terminate FD start FB frame data frame data frame data preamble preamble preamble preamble preamble Related Information Avalon Interface Specifications SDR XGMII TX Interface This sectio...

Page 153: ... 36 44 Lane 1 16 9 17 52 45 53 Lane 2 25 18 26 61 54 62 Lane 3 34 27 35 70 63 71 xgmii_rx_clk Output The XGMII SDR RX clock which runs at 156 25 MHz Transceiver Serial Data Interface This section describes the signals in the XAUI transceiver serial data interface The XAUI transceiver serial data interface has four lanes of serial data for both the TX and RX interfaces This interface runs at 3 125 ...

Page 154: ...n pll_ref_clk Input This is a 156 25 MHz reference clock that is used by the TX PLL and CDR logic rx_analogreset Input This signal resets the analog CDR and deserializer logic in the RX channel It is available only for the hard IP implementation rx_digitalreset Input PCS RX digital reset signal It is available only for the hard IP implementation tx_digitalreset Input PCS TX digital reset signal If...

Page 155: ...n cal_blk_powerdown Input Powers down the calibration block A high to low transition on this signal restarts calibration Only available in Arria II GX HardCopy IV and Stratix IV GX and Stratix IV GT devices gxb_powerdown Input When asserted powers down the entire transceiver block Only available in Arria II GX HardCopy IV and Stratix IV GX and Stratix IV GT devices pll_powerdown Input Powers down ...

Page 156: ...d 10 bit code group has a code violation or disparity error It is used along with the rx_disperr signal to differentiate between a code violation error a disparity error or both The rx_ errdetect signal is 2 bits wide per channel for a total of 8 bits per XAUI link rx_syncstatus 7 0 Output Synchronization indication RX synchroniza tion is indicated on the rx_syncstatus port of each channel The rx_...

Page 157: ...le 1 Enables serial loopback 0 Disables serial loopback This signal is asynchronous to the receiver The status of the serial loopback option is recorded by the PMA channel controller word address 0x061 rx_channelaligned Output When asserted indicates that the RX channel is aligned pll_locked Output In LTR mode indicates that the receiver CDR has locked to the phase and frequency of the input refer...

Page 158: ...isparity of the 8B 10B decoded byte is negative Low when the current running disparity of the 8B 10B decoded byte is positive rx_syncstatus 7 0 Output Synchronization indication RX synchronization is indicated on the rx_syncstatus port of each channel The rx_syncstatus signal is 2 bits wide per channel for a total of 8 bits per XAUI link rx_phase_comp_fifo_ error 3 0 Output Indicates a RX phase co...

Page 159: ...serted high phy_mgmt_waitrequest Output When asserted indicates that the Avalon MM slave interface is unable to respond to a read or write request When asserted control signals to the Avalon MM slave interface must remain constant For more information about the Avalon MM interface including timing diagrams refer to the Avalon Interface Specifications The following table specifies the registers tha...

Page 160: ...d Reading bit 0 returns the status of the reset controller TX ready bit Reading bit 1 returns the status of the reset controller RX ready bit This bit self clears Reset Controls Manual Mode 0x044 31 4 0 RW Reserved It is safe to write 0s to reserved bits 1 RW reset_tx_digital Writing a 1 causes the internal TX digital reset signal to be asserted resetting all channels enabled in reset_ch_bitmask Y...

Page 161: ...at the RX CDR has changed from LTR to LTD mode Bit n corresponds to channel n 0x067 31 0 RO pma_rx_is_lockedtoref When asserted indicates that the RX CDR PLL is locked to the reference clock Bit n corresponds to channel n XAUI PCS 0x082 31 4 Reserved 3 0 RW invpolarity 3 0 Inverts the polarity of corresponding bit on the RX interface Bit 0 maps to lane 0 and so on This register is only available i...

Page 162: ... 0 3 Reading the value of the syncstatus register clears the bits From block Word aligner 0x085 31 16 Reserved 15 8 R errdetect 7 0 When set indicates that a received 10 bit code group has an 8B 10B code violation or disparity error It is used along with disperr to differentiate between a code violation error a disparity error or both There are 2 bits per RX channel for a total of 8 bits per XAUI ...

Page 163: ...rd XAUI implementation From block Word aligner 0x087 31 16 Reserved 15 8 R sticky rmfifodatainserted 7 0 When asserted indicates that the RX rate match block inserted a R column Goes high for one clock cycle per inserted R column Reading the value of the rmfifoda tainserted register clears the bits This register is only available in the hard XAUI implementation From block Rate match FIFO 7 0 rmfif...

Page 164: ...orresponding lane Reading the value of the phase_comp_fifo_error register clears the bits This register is only available in the hard XAUI implementation From block TX phase compensation FIFO 0x08a 0 RW simulation_flag Setting this bit to 1 shortens the duration of reset and loss timer when simulating Altera recommends that you keep this bit set during simulation For more information about the ind...

Page 165: ...the Transceiver Reconfiguration IP Core The size of this bus is depends on the device For the soft PCS in Stratix IV GX and GT devices n 68 bits For hard XAUI variants n 16 For Stratix V devices the number of bits depends on the number of channels specified Refer to Chapter 16 Transceiver Reconfiguration Controller IP Core for more information Related Information Transceiver Reconfiguration Contro...

Page 166: ...Restriction If you are using 6 or N bonding transceiver dynamic reconfiguration requires that you assign the starting channel number Logical channel 0 should be assigned to either physical transceiver channel 1 or channel 4 of a transceiver bank However if you have already created a PCB with a different lane assignment for logical lane 0 you can use the workaround shown in the following example to...

Page 167: ... page 16 1 SDC Timing Constraints The SDC timing constraints and approaches to identify false paths listed for Stratix V Native PHY IP apply to all other transceiver PHYs listed in this user guide Refer to SDC Timing Constraints of Stratix V Native PHY for details Related Information SDC Timing Constraints of Stratix V Native PHY on page 12 74 This section describes SDC examples and approaches to ...

Page 168: ...s which are striped round robin across the lanes to reduce latency Striping renders the interface independent of exact lane count The protocol accepts packets on 256 logical channels and is expandable to accommodate up to 65 536 logical channels Packets are split into small bursts which can optionally be interleaved The burst semantics include integrity checking and per channel flow control 2015 A...

Page 169: ...en for Stratix V Devices for a reference design that implements the Interlaken protocol in a Stratix V device Related Information Interlaken Protocol Specification Rev 1 2 Avalon Interface Specifications Transceiver Configurations in Stratix V Devices Transceiver Configurations in Arria V Devices PHY IP Design Flow with Interlaken for Stratix V Devices Interlaken PHY Device Family Support This sec...

Page 170: ...rameter Value Description Device family Arria V GZ Stratix V Specifies the device family Datapath mode Duplex RX TX Specifies the mode of operation as Duplex RX or TX mode Lane rate 3125 Mbps 5000 Mbps 6250 Mbps 6375 Mbps 10312 5 Mbps 10312 5 Mbps 12500 Mbps Custom Specifies the lane data rate The Input clock frequency and Base data rate parameters update automatically based on the Lane rate you s...

Page 171: ...e rate 10 Lane rate 8 Specifies the frequency of the input reference clock The default value for the Input clock frequency is the Lane rate 20 Many reference clock frequencies are available PLL type CMU ATX Specifies the PLL type The CMU PLL has a larger frequency range than the ATX PLL The ATX PLL is designed to improve jitter performance and achieves lower channel to channel skew however it supp...

Page 172: ...le These optional signals report the status of word and synchronization locks and CRC32 errors Refer to Avalon ST RX Signals for more information Create tx_coreclkin port On Off The tx_coreclkin drives the write side of TX FIFO This clock is required for multi lane synchroniza tion but is optional for single lane Interlaken links If tx_coreclkin is deselected for single lane Interlaken links tx_us...

Page 173: ...0 phy_mgmt_writedata 31 0 phy_mgmt_readdata 31 0 phy_mgmt_write phy_mgmt_read phy_mgmt_waitrequest pll_ref_clk InterlakenTop Level Signals tx_serial_data n rx_serial_data n Avalon ST TX to from MAC High Speed Serial I O PLL Avalon MM PHY Management Interface Avalon ST RX from to MAC Dynamic Reconfiguation tx_coreclkin rx_coreclkin reconfig_to_xcvr n 70 1 0 reconfig_from_xcvr n 46 1 0 FIFO Clock In...

Page 174: ...serted tx_parallel_data n 63 0 is a control word The value of header synchronization bits 65 64 of the Interlaken word identify whether bits 63 0 are a Framing Layer Control Burst IDLE Control Word or a data word The MAC must gray encode the header synchronization bits The value 2 b10 indicating Burst IDLE Control Word must be gray encoded to the value 1 b1 for tx_parallel_data n 64 The value 2 b0...

Page 175: ...is ready for service The tx_ ready latency for the TX interface is 0 A 0 latency means that the TX FIFO can accept data on the same clock cycle that tx_ready is asserted This output is synchronous to the phy_mgmt_clk clock domain The Interlaken MAC must wait for tx_ready before initiating data transfer pre fill pattern or valid user data on any lanes The TX FIFO only captures input data from the I...

Page 176: ...one can be asserted Do not use valid data to pre fill the TX FIFO Use the following Verilog HDL assignment for Quartus II releases prior to 12 0 assign tx_parallel_data 65 tx_sync_ done 1 b1 tx_datain_bp 0 tx_clkout Output For single lane Interlaken links tx_user_clkout is available when you do not create the optional tx_ coreclkin For Interlaken links with more than 1 lane tx_coreclkin is require...

Page 177: ...t and phy_mgmt_clk_reset to initiate the synchroniza tion sequence on the TX lanes After tx_sync_done is asserted you must never allow the TX FIFO to underflow doing so requires you to hard reset to the Interlaken PHY IP Core For Quartus versions prior to 12 0 you must pre fill the TX FIFO before tx_sync_done can be asserted Use the following Verilog HDL assignment for Quartus II releases prior to...

Page 178: ...indicating data word is gray encoded to the value 1 b0 and rx_ parallel_data n 65 is deasserted by the Interlaken Receive PCS The Framing Layer Control Words Frame Sync Scrambler State Skip and Diag are not discarded but are sent to the Interlaken MAC for multi lane alignment and deskew on the lanes rx_parallel_data n 66 Output This is an active high synchronous status signal indicating that block...

Page 179: ...elow You can tie this signal s inverted logic to the rx_dataout_bp n receive FIFO read enable signal as the following assignment statement illustrates assign rx_dataout_bp 0 rx_parallel_data 68 rx_parallel_data n 69 Output When asserted indicates that the RX FIFO has found the first Interlaken synchronization word alignment pattern For very short metaframes this signal may be asserted after the fr...

Page 180: ...ed in the next clock cycle rx_parallel_data n 71 Output When asserted indicates a CRC32 error in this lane This signal is optional This output is synchronous to the rx_clkout clock domain rx_ready Output When asserted indicates that the RX interface has exited the reset state and is ready for service The Interlaken MAC must wait for rx_ready to be asserted before initiating data transfer on any la...

Page 181: ...ignment statement assign rx_dataout_bp 0 rx_parallel_data 68 rx_user_clkout Output Master channel rx_user_clkout is available when you do not create the optional rx_coreclkin Interlaken PHY TX and RX Serial Interface This section describes the signals in the chip to chip serial interface Table 7 6 Serial Interface Signal Name Direction Description tx_serial_data Output Differential high speed seri...

Page 182: ... FIFO Altera recommends using this clock to reduce clock skew The minimum frequency is data rate 67 Using a lower frequency will underflow the TX FIFO causing the Frame Generators to go into a unrecoverable out of alignment state and insert Skip Words into the lane If the Interlaken TX FIFO underflows the alignment state machine tries to recover continuously When disabled tx_clkout drives the writ...

Page 183: ...P Core the Transceiver PHY Reconfiguration Controller mgmt_rst_reset signal must be simultaneously asserted with the phy_mgmt_clk_reset signal to bring the Frame Generators in the link into alignment This is a mandatory requirement Failure to comply to this requirement will result in excessive transmit lane to lane skew in the Interlaken link phy_mgmt_addr 8 0 Input 9 bit Avalon MM address phy_mgm...

Page 184: ...d use of a soft reset or the use of these reset register bits for Interlaken PHY IP 0x042 1 0 WO reset_control write Writing a 1 to bit 0 initiates a TX digital reset using the reset controller module The reset affects channels enabled in the reset_ch_bitmask Writing a 1 to bit 1 initiates a RX digital reset of channels enabled in the reset_ch_bitmask RO reset_status read Reading bit 0 returns the...

Page 185: ...reset_ch_bitmask You must write a 0 to clear the reset condition 1 RW reset_tx_digital Writing a 1 causes the internal TX digital reset signal to be asserted resetting all channels enabled in reset_ ch_bitmask You must write a 0 to clear the reset condition PMA Control and Status Registers 0x061 31 0 RW phy_serial_loopback Writing a 1 to channel n puts channel n in serial loopback mode For informa...

Page 186: ..._addr Provides for indirect addressing of all PCS control and status registers Use this register to specify the logical channel address of the PCS channel you want to access Device Registers 27 RO rx_crc32_err Asserted by the CRC32 checker to indicate a CRC error in the corresponding RX lane From block CRC32 checker 0x081 25 RO rx_sync_lock Asserted by the frame synchronizer to indicate that 4 fra...

Page 187: ...n interface for each channel and TX PLL in your design when the Quartus II software compiles your design it reduces the number of reconfiguration interfaces by merging reconfiguration interfaces The synthesized design typically includes a reconfigura tion interface for at least three channels because three channels share an Avalon MM slave interface which connects to the Transceiver Reconfiguratio...

Page 188: ... PHY IP apply to all other transceiver PHYs listed in this user guide Refer to SDC Timing Constraints of Stratix V Native PHY for details Related Information SDC Timing Constraints of Stratix V Native PHY on page 12 74 This section describes SDC examples and approaches to identify false timing paths Interlaken PHY Simulation Files and Example Testbench This section describes the Interlaken PHY sim...

Page 189: ... GX devices Figure 8 2 illustrates the top level blocks of the Gen1 and Gen2 IP cores As these figures illustrate the PIPE interface connects to a third party MAC PHY implemented using soft logic in the FPGA fabric The reconfiguration buses connect to the Transceiver Reconfiguration Controller IP Core For more informa tion about this component refer to Transceiver Reconfiguration Controller IP Cor...

Page 190: ...rriaV GZ or StratixV GX PCS TX RX Phase Comp FIFO Byte Serialzier Deserializer 8B 10B Rate Match FIFO Word Aligner PMA Analog Buffers SERDES 10 bit Interface Avalon MM Cntrl Status Avalon ST PIPE to ASIC ASSP FPGA PCIe Link Transceiver Reconfiguration Controller Embedded Controller Reconfiguration to from XCVR PCIeTransaction Data Link Physical Layers Soft Logic For more detailed information about...

Page 191: ...logic it uses less than 1 of the available adaptive logic modules ALMs memory primary and secondary logic registers Parameterizing the PHY IP Core for PCI Express PIPE Complete the following steps to configure the PHY IP Core for PCI Express in the MegaWizard Plug In Manager 1 Under Tools IP Catalog select the device family of your choice 2 Under Tools IP Catalog Interfaces PCI Express selectPHY I...

Page 192: ...3 implements the PHY Interface for the PCI Express Architecture PCI Express 3 0 specifi cation Gen1 and Gen2 base data rate 1 Lane rate 2 Lane rate 4 Lane rate 8 Lane rate The base data rate is the output clock frequency of the TX PLL Select a base data rate that minimizes the number of PLLs required to generate all the clocks required for data transmission Data rate 2500 Mbps 5000 Mbps 8000 Mbps ...

Page 193: ...ates above 6 Gbps PLL reference clock frequency 100 MHz 125 MHz You can use either the 100 MHz or 125 MHz input reference clock The PCI Express specifications require an 100 MHz reference clock FPGA transceiver width 8 16 32 Specifies the width of the interface between the PHY MAC and PHY PIPE The following options are available Gen1 8 or 16 bits Gen2 16 bits Gen3 32 bits Using the Gen1 16 bit int...

Page 194: ...E Output to MAC PHY Clocks Status pipe_txdata 31 0 15 0 7 0 pipe_txdatak 3 0 1 0 0 pipe_txcompliance n 1 0 pipe_tx_data_valid n 1 0 tx_blk_start 3 0 tx_sync_hdr 1 0 pipe_txdetectrx_loopback n 1 0 pipe_txelecidle n 1 0 pipe_powerdown 2 n 1 0 pipe_g3_txdeemph 17 0 pipe_txmargin 2 n 1 0 pipe_txswing pipe_rxpolarity n 1 0 pipe_rate 1 0 rx_eidleinfersel 2 n 1 0 pipe_rxpresethint 2 0 pipe_rxdata 31 0 15...

Page 195: ...32 bits represent the 4 symbols of TX data Bits 23 16 are the third symbol to be transmitted and bits 31 24 are the fourth symbol pipe_txdatak 3 0 1 0 or 0 Input For Gen1 and Gen2 data and control indicator for the received data When 0 indicates that pipe_ txdata is data when 1 indicates that pipe_ txdata is control For Gen3 Bit 0 corresponds to pipe_ txdata 7 0 bit 1 corresponds to pipe_ txdata 1...

Page 196: ...e PHY to start a receive detection operation After power up asserting this signal starts a loopback operation Refer to section 6 4 of the Intel PHY Interface for PCI Express PIPE for a timing diagram pipe_txelecidle Input This signal forces the transmit output to electrical idle Refer to section 7 3 of the Intel PHY Interface for PCI Express PIPE for timing diagrams pipe_powerdown n 1 0 Input This...

Page 197: ...l swing 800 1200 mV Half swing 400 700 mV 3 b010 3 b011 Reserved 3 b100 3 b111 If last value full swing 200 400 mV half swing 100 200 mV else reserved pipe_txswing Input Indicates whether the transceiver is using full or low swing voltages as defined by the tx_ pipemargin 1 b0 Full swing 1 b1 Low swing pipe_rxpolarity Input When 1 instructs the PHY layer to invert the polarity on the received data...

Page 198: ... Absence of Electrical Idle exit in 128 ms window for Gen1 pipe_rxpresethint 2 0 Input Provides the RX preset hint for the receiver Only used for the Gen3 data rate Table 8 4 Preset Mappings to TX De Emphasis Preset C 1 C0 C 1 1 001001 011010 000000 2 000110 011101 000000 3 000111 011100 000000 4 000101 011110 000000 5 000000 100011 000000 6 000000 011111 000100 7 000000 011110 000101 8 000111 011...

Page 199: ...ntrol indicator for the source data When 0 indicates that pipe_rxdata is data when 1 indicates that pipe_rxdata is control Bit 0 corresponds to byte 0 Bit 1 corresponds to byte 1 and so on rx_blk_start 3 0 Output For Gen3 operation indicates the block starting byte location in the received 32 bits data of the 130 bits block data Data reception must start in bits 7 0 of the 32 bit data word so that...

Page 200: ...owing encodings are defined 3 b000 receive data OK 3 b001 1 SKP added 3 b010 1 SKP removed 3 b011 Receiver detected 3 b100 Both 8B 10B or 128b 130b decode error and optionally RX disparity error 3 b101 Elastic buffer overflow 3 b110 Elastic buffer underflow 3 b111 Receive disparity error not used if disparity error is reported using 3 b100 pipe_phystatus Output This signal is used to communicate c...

Page 201: ...e PCS interface widths Doubling the FPGA transceiver width haves the required frequency Table 8 7 pipe_pclk Frequencies Capability FPGA Transceiver Width Gen1 Gen2 Gen3 Gen1 only 8 bits 250 MHz 16 bits 125 MHz Gen2 capable 16 bits 125 MHz 250 MHz Gen3 capable 32 bits 62 5 MHz 125 MHz 250 MHz PHY for PCIe PIPE Clock SDC Timing Constraints for Gen3 Designs For Gen3 designs you must add the following...

Page 202: ... interface has exited the reset state and is ready to receive pll_locked p 1 0 Output When asserted indicates that the TX PLL is locked to the input reference clock This signal is asynchronous rx_is_lockedtodata n 1 0 Output When asserted the receiver CDR is in to lock to data mode When deasserted the receiver CDR lock mode depends on the rx_locktorefclk signal level rx_is_lockedtoref n 1 0 Output...

Page 203: ...fer to the Channel Placement Gen1 and Gen2 and Channel Placement Gen3 sections in the Stratix V Hard IP for PCI Express User Guide Related Information Transceiver Configurations in Arria V GZ Devices Transceiver Configurations in Stratix V Devices Stratix V Hard IP for PCI Express User Guide PHY for PCIe PIPE Register Interface and Register Descriptions The Avalon MM PHY management interface provi...

Page 204: ... Signal Name Direction Description phy_mgmt_clk Input Avalon MM clock input There is no frequency restriction for Stratix V devices however if you plan to use the same clock for the PHY management interface and transceiver reconfiguration you must restrict the frequency range of phy_mgmt_clk to 100 125 MHz to meet the specification for the transceiver reconfiguration clock phy_mgmt_clk_reset Input...

Page 205: ...ates that the TX CMU PLL P is locked to the input reference clock There is typically one pma_tx_pll_is_locked bit per system Reset Control Registers Automatic Reset Controller 0x041 31 0 RW reset_ch_bitmask Reset controller channel bitmask for digital resets The default value is all 1s Channel n can be reset when bit n 1 0x042 1 0 W reset_control write Writing a 1 to bit 0 initiates a TX digital r...

Page 206: ...1 RW reset_tx_digital Writing a 1 causes the internal TX digital reset signal to be asserted resetting all channels enabled in reset_ch_bitmask You must write a 0 to clear the reset condition Refer to Timing Constraints for Reset Signals when Using Bonded PCS Channels for a SDC constraint you must include in your design 0 RW pll_powerdown Writing a 1 causes the internal TX PLL to powerdown If you ...

Page 207: ...mber Specifies lane or group number for indirect addressing which is used for all PCS control and status registers For variants that stripe data across multiple lanes this is the logical group number For non bonded applications this is the logical lane number 0x081 31 6 R Reserved 5 1 R rx_bitslipboundaryselectout Records the number of bits slipped by the RX Word Aligner to achieve word alignment ...

Page 208: ...this register transitions from 0 to 1 the RX data slips a single bit From block Word aligner 2 RW rx_bytereversal_enable When set enables byte reversal on the RX interface From block Word aligner 1 RW rx_bitreversal_enable When set enables bit reversal on the RX interface From blockk Word aligner 0 RW rx_enapatternalign When set the word alignment logic operates in pattern detect mode From block W...

Page 209: ...e between a code violation error and a disparity error or both In PIPE mode the PIPE specific output port called pipe_rxstatus encodes the errors From block 8B 10B decoder For more information about the individual PCS blocks refer to Transceiver Architecture in Stratix V Devices in the Stratix V Device Handbook Related Information Transceiver Architecture in Stratix V Devices PHY for PCIe PIPE Lin...

Page 210: ... bits set to 2 b01 in order to move to EQ Phase 1 Phase 1 During Phase 1 of equalization process the link partners exchange FS Full Swing and LF Low Frequency information These values represent the upper and lower bounds for the TX coefficients The receiver uses this information to calculate and request the next set of transmitter coefficients 1 Once training sets with EC bits set to 1 b0 are capt...

Page 211: ...e for PCI Express PIPE PCI Express as a Root Port you cannot perform Phase 3 tuning Once Phase 3 tuning is complete the Root Port moves to Recovery RcvrLock sending EC 2 b00 along with the final coefficients or preset agreed upon in Phase 2 The Endpoint moves to Recovery RcvrLock using the final coefficients or preset agreed upon in Phase 3 Recommendations for Tuning Link Partner s Transmitter Thi...

Page 212: ... initially create a separate reconfiguration interface for each channel and TX PLL in your design when the Quartus II software compiles your design it reduces the total number of reconfigu ration interfaces by merging reconfiguration interfaces The synthesized design typically includes a reconfiguration interface for at least three channels because the three channels within each transceiver triple...

Page 213: ...l lane 1 you can use the workaound shown in the example below to remove this restriction the example redefines the pma_bonding_master parameter using the Quartus II Assignment Editor In this example the pma_bonding_master was originally assigned to physical channel 1 The original assignment could also have been to physical channel 4 The to parameter reassigns the pma_bonding_master to the PHY IP C...

Page 214: ...et 1 25 and 2 50 Gbps Serial RapidIO SRIO 1 3 Serial ATA SATA and serial attached SCSI SAS Gen1 Gen2 and Gen3 Gigabit capable passive optical network GPON 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All...

Page 215: ...ces Device Family Support IP cores provide either final or preliminary support for target Altera device families These terms have the following definitions Final support Verified with final timing models for this device Preliminary support Verified with preliminary timing models for this device Table 9 1 Device Family Support Device Family Support Arria V devices Hard PCS and PMA Final Cyclone V d...

Page 216: ... page 9 14 g Analog Parameters on page 9 16 5 Click Finish to generate your parameterized Custom PHY IP Core General Options Parameters The General Options tab allows you to set the basic parameters of your transceiver PHY Table 9 3 Table 9 3 Custom PHY General Options Name Value Description Device family Arria V Cyclone V Stratix V Specifies the device family Arria V Cyclone V and Stratix V are a...

Page 217: ...he N clock network Select fb_compensation feedback compensation to use the same clock source for multiple channels across different transceiver banks to reduce clock skew This option is only available for Stratix V devices For more information about bonding refer to Transmitter Clock Network in Transceiver Clocking in Arria V Devices in volume 2 of the Arria V Device Handbook For more information ...

Page 218: ...signed to improve jitter performance and achieves lower channel to channel skew however it supports a narrower range of data rates and reference clock frequencies Another advantage of the ATX PLL is that it does not use a transceiver channel while the CMU PLL does Because the CMU PLL is more versatile it is specified as the default setting An informational message displays in the message pane tell...

Page 219: ...d aligner is operational Create rx_coreclkin port On Off This is an optional clock to drive the coreclk of the RX PCS Create tx_coreclkin port On Off This is an optional clock to drive the coreclk of the TX PCS Create rx_recovered_clk port On Off When enabled the RX recovered clock is an output Create optional ports On Off When you turn this option on the following signals are added to the top lev...

Page 220: ...1 If either the pma_rx_set_locktodata and pma_rx_ set_locktoref is set the CDR automatic lock mode is disabled Table 9 4 Reset Mode The CDR can be put in either manual or automatic mode The CDR mode is controlled with the pma_rx_set_locktodata and pma_rx_set_locktoref registers This table shows the required settings to control the CDR mode rx_set_locktoref rx_set_locktodata CDR Lock Mode 1 0 Manua...

Page 221: ...rammable state machine This mode can only be used with 8B 10B encoding The data width at the word aligner can be 10 or 20 bits You can specify the following parameters Number of consecutive valid words before sync state is reached Specifies the number of consecutive valid words needed to reduce the built up error count by 1 Valid values are 1 256 Number of bad data words before loss of sync state ...

Page 222: ...r pattern 16 Manual alignment 8 16 32 User controlled signal starts alignment process Alignment occurs once unless signal is re asserted 20 Manual alignment 7 10 20 User controlled signal starts alignment process Alignment occurs once unless signal is re asserted Automatic Synchronized State Machine 7 10 20 Automatically selected word aligner pattern length and pattern Related Information Transcei...

Page 223: ...attern 0010111100 0101111100 Enter a 10 bit skip pattern bits 10 19 and a 10 bit control pattern bits 0 9 The skip pattern must have neutral disparity Create optional rate match FIFO status ports On Off When enabled creates the rx_ rmfifoddatainserted and rx_ rmfifodatadeleted signals from the rate match FIFO become output ports Note If you have the auto negotiation state machine in your transceiv...

Page 224: ...to include the 8B 10B rx_errdetect and rx_disperr error signals at the top level of the Custom PHY IP Core Byte Order Parameters The byte ordering block is available when the PCS width is doubled at the byte deserializer Byte ordering identifies the first byte of a packet by determining whether the programmed start of packet SOP pattern is present it inserts enough pad characters in the data strea...

Page 225: ...rface Word aligner in automatic synchroni zation state machine mode Configuration 3 32 bit FPGA fabric transceiver interface No 8B 10B decoder 16 bit PMA PCS interface Word aligner in manual alignment mode Configuration 4 32 bit FPGA fabric transceiver interface 8B 10B decoder 20 bit PMA PCS interface Word aligner in manual alignment mode Configuration 5 40 bit FPGA fabric transceiver interface No...

Page 226: ...ribed in the Enable byte ordering block Configuration 1 8 bits Configuration 2 10 bits For example If you select a Kx y control code group as the byte ordering pattern the most significant 2 bits of the 10 bit byte ordering pattern must be 2 b01 If you select a Dx y data code group as the byte ordering pattern the most significant 2 bits of the 10 bit byte ordering pattern must be 2 b00 The least ...

Page 227: ...multiple data rates If your design does not require transceiver TX PLL dynamic reconfiguration set this value to 1 The number of actual physical PLLs that are implemented depends on the selected clock network Each channel can dynamically select between n PLLs where n is the number of PLLs specified for this parameter You must disable the embedded reset controller and design your own controlled res...

Page 228: ... corresponds to input clock 0 and so on TX PLL 0 3 PLL Type CMU ATX Specifies the PLL type PLL base data rate 1 Lane rate 2 Lane rate 4 Lane rate Specifies Base data rate Reference clock frequency Variable Specifies the frequency of the PLL input reference clock The PLL must generate an output frequency that equals the Base data rate 2 You can use any Input clock frequency that allows the PLLs to ...

Page 229: ...ons for your device Related Information Analog Settings for Arria V Devices on page 19 2 Analog Settings for Arria V GZ Devices on page 19 11 Analog Settings for Cyclone V Devices on page 19 26 Analog Settings for Stratix V Devices on page 19 34 Presets for Ethernet Presets allow you to specify a group of parameters to implement a particular protocol or application If you apply the presets for GIG...

Page 230: ...of consecutive valid words before sync state is reached 3 3 Number of bad data words before loss of sync state 3 3 Number of valid patterns before sync state is reached 3 3 Create optional word aligner status ports Off Off Word aligner pattern length 10 10 Word alignment pattern 0101111100 0101111100 Enable run length violation checking Off Off Run length Rate Match Options Enable rate match FIFO ...

Page 231: ...ontrol Off Off Create optional 8B 10B status port Off Off Byte Order Options Enable byte ordering block Off Off Enable byte ordering block manual control Off Off Byte ordering pattern Byte ordering pad pattern 9 18 Presets for Ethernet UG 01080 2015 01 19 Altera Corporation Custom PHY IP Core Send Feedback ...

Page 232: ...n 1 0 rx_bitslipboundaryselectout n 5 1 0 rx_patterndetect n w s 1 0 rx_rmfifodatainserted n 1 0 rx_rmfifodatadeleted n 1 0 rx_rlv n 1 0 rx_recovered_clk n 1 0 rx_byteordflag n 1 0 pll_powerdown tx_digitalreset n 1 0 tx_analogreset n 1 0 tx_cal_busy n 1 0 rx_digitalreset n 1 0 rx_analogreset n 1 0 rx_cal_busy n 1 0 reconfig_to_xcvr n 70 1 0 reconfig_from_xcvr n 46 1 0 Avalon STTx from MAC Speed Se...

Page 233: ...ansceiver interface width If 8B 10B encoding is disabled when you have enabled dynamic reconfiguration the following mapping applies to each word tx_parallel_data 7 0 Data input bus tx_parallel_data 10 8 Unused Refer to Table 9 13 for the location of valid data for a single and double word data buses with and without the byte serializer tx_clkout Output This is the clock for TX parallel data contr...

Page 234: ...wice the data width of the PMA This feature allows the PCS to run at a lower frequency and accommodates a wider range of FPGA interface widths Configuration Bus Used Bits Single word data bus byte deserializer disabled 10 0 word 0 Single word data bus byte serializer enabled 32 22 10 0 words 0 and 2 Double word data bus byte serializer disabled 21 0 words 0 and 1 Double word data bus byte serializ...

Page 235: ...t rx_parallel_data 14 13 2 b00 Normal data 2 b01 Deletion 2 b10 Insertion or Underflow with 9 h1FE or 9 h1F7 2 b11 Overflow rx_parallel_data 14 13 Running disparity value If 8B 10B decoding is disabled the width of this interface is width you specified for FPGA fabric transceiver interface width If 8B 10B encoding is disabled when you have enabled dynamic reconfi guration the following mapping app...

Page 236: ...alizer for single and double word FPGA fabric to PCS interface widths The byte deserializer allows the PCS to operate at twice the data width of the PMA This feature allows the PCS to run at a lower frequency and accommodates a wider range of FPGA interface widths Configuration Location of rx_parallel_data Single word data bus byte deserializer disabled 15 0 word 0 Single word data bus byte serial...

Page 237: ...en asserted indicates that the RX interface has exited the reset state and is ready to receive pll_locked p 1 0 Output When asserted indicates that the PLL is locked to the input reference clock tx_forceelecidle n 1 0 Input When asserted enables a circuit to detect a downstream receiver It is used for the PCI Express protocol This signal must be driven low when not in use because it causes the TX ...

Page 238: ...gnal is optional rx_signaldetect n 1 0 Output Signal threshold detect indicator required for the PCI Express protocol When asserted it indicates that the signal present at the receiver input buffer is above the programmed signal detection threshold value rx_bitslip n 1 0 Input Used for manual control of bit slipping The word aligner slips a bit of the current word for every rising edge of this sig...

Page 239: ... These signals are available if you do not enable the embedded reset controller Table 9 19 Avalon ST RX Interface Signal Name Direction Description pll_powerdown Input When asserted resets the TX PLL tx_digitalreset n 1 0 Input When asserted reset all blocks in the TX PCS If your design includes bonded TX PCS channels refer to Timing Constraints for Reset Signals when Using Bonded PCS Channels for...

Page 240: ...iguration controller is reset It will not be asserted if you manually re trigger the calibration IP Related Information Timing Constraints for Bonded PCS and PMA Channels on page 17 10 Transceiver Reset Control in Stratix V Devices Transceiver Reset Control in Arria V Devices Transceiver Reset Control in Cyclone V Devices Register Interface and Register Descriptions The Avalon MM PHY management in...

Page 241: ...gnal Name Direction Description phy_mgmt_clk Input Avalon MM clock input There is no frequency restriction for the phy_ mgmt_clk however if you plan to use the same clock for the PHY management interface and transceiver reconfiguration you must restrict the frequency range of phy_ mgmt_clk to 100 150 MHz to meet the specification for the transceiver reconfiguration clock phy_mgmt_clk_reset Input G...

Page 242: ...erved or undefined register addresses may have undefined side effects PMA Common Control and Status Registers Table 9 21 PMA Common Control and Status Registers Word Addr Bits R W Register Name Description 0x022 31 0 R pma_tx_pll_is_locked Bit P indicates that the TX CMU PLL P is locked to the input reference clock There is typically one pma_tx_pll_is_ locked bit per system Reset Control Registers...

Page 243: ...reset sequence If you disable Enable embedded reset controller on the General Options tab of the MegaWizard Plug In Manager you can design your own reset sequence using the tx_analogreset rx_analogreset tx_digitalreset rx_digitalreset and pll_powerdown which are top level ports of the Custom Transceiver PHY By default the CDR circuitry is in automatic lock mode whether you use the embedded reset c...

Page 244: ...al loopback mode 0x063 31 0 R pma_rx_signaldetect When channel n 1 indicates that receive circuit for channel n senses the specified voltage exists at the RX input buffer 0x064 31 0 RW pma_rx_set_locktodata When set programs the RX CDR PLL to lock to the incoming data Bit n corresponds to channel n 0x065 31 0 RW pma_rx_set_locktoref When set programs the RX CDR PLL to lock to the reference clock B...

Page 245: ...block Word aligner 0 R rx_phase_comp_fifo_error When set indicates an RX phase compensation FIFO error From block RX phase Compensation FIFO 0x082 0 RW tx_phase_comp_fifo_error When set indicates an TX phase compensation FIFO error From block TX phase Compensation FIFO 0x083 5 1 RW tx_bitslipboundary_ select Sets the number of bits that the TX bit slipper needs to slip To block Word aligner 0 RW t...

Page 246: ...process voltage and temperature PVT These process variations result in analog voltages that can be offset from required ranges The calibration performed by the dynamic reconfiguration interface compensates for variations due to PVT Each channel and each TX PLL have separate dynamic reconfiguration interfaces The MegaWizard Plug In Manager provides informational messages on the connectivity of thes...

Page 247: ...el 1 or channel 4 of a transceiver bank However if you have already created a PCB with a different lane assignment for logical lane 0 you can use the workaound shown in the following example to remove this restriction The example redefines the pma_bonding_master parameter using the Quartus II Assignment Editor In this example the pma_bonding_master was originally assigned to physical channel 1 The...

Page 248: ... the Stratix V GX Device Configurations section in the Transceiver Configurations in Stratix V Devices chapter of the Stratix V Device Handbook Related Information Transceiver Configurations in Stratix V Devices 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U...

Page 249: ...The following table shows the typical expected device resource utilization for different configurations using the current version of the Quartus II software targeting a Stratix V GX 5SGSMD612H35C2 device Table 10 2 Low Latency PHY Performance and Resource Utilization Stratix V GX Device Implementa tion Number of Lanes Serialization Factor Worst Case Frequency Combinational ALUTs Dedicated Register...

Page 250: ...apath 10 8 10 16 or 20 667 67 193 171 0 Parameterizing the Low Latency PHY Complete the following steps to configure the Low Latency PHY IP Core in the MegaWizard Plug In Manager 1 Under Tools IP Catalog select Stratix V as the device family 2 Under Tools IP Catalog Interface Protocols Transceiver PHY select Low Latency PHY 3 Use the tabs on the MegaWizard Plug In Manager to select the options req...

Page 251: ...e the option of using either the Standard datapath which is the default mode or changing to the 10G datapath by selecting this option Refer to Table 10 4 Datapath Width Support for a comprehen sive list of datapath support Mode of operation Duplex RX TX Specifies the mode of operation as Duplex RX or TX mode Number of lanes 1 32 Specifies the total number of lanes in each direction Stratix V devic...

Page 252: ... single width of 128 bits Refer to Table 10 4 Datapath Width Support for the supported interface widths of the Standard and 10G datapaths PCS PMA interface width 8 10 16 20 32 30 64 The PCS PMA interface width depends on the FPGA fabric transceiver interface width and the Datapath type Refer to Datapath Width Support for the supported interface widths of the Standard and 10G datapaths PLL type CMU...

Page 253: ...ct fb_compensation as the bonding mode then the input reference clock frequency is limited to the data rate PCS PMA interface width The following table lists Standard and 10G datapath widths for the FPGA fabric transceiver interface the PCS PMA interface and the resulting frequencies for the tx_clkout and rx_clkout parallel clocks In almost all cases the parallel clock frequency is described by th...

Page 254: ...ed by the Low Latency PHY is the data rate 40 You must generate a 50 frequency clock from the 40 clock and feed this clock back into the tx_ coreclkin The rx_clkout frequency generated by the Low Latency PHY is 40 of the data rate You must generate a 50 frequency from the recovered clock and feed this back into the rx_coreclkin 7 For this datapath configuration the tx_clkout frequency generated by...

Page 255: ... TX and RX channels The reference clock pins for each channel must reside in the same transceiver bank For more information refer to the FPGA Fabric Transceiver Interface Clocking section in the Stratix V Transceiver Clocking chapter Enable rx_coreclkin On Off When you turn this option on rx_coreclkin connects to the read clock of the RX phase compensation FIFO and you can clock the parallel RX ou...

Page 256: ...in bitslip mode This option is available for Stratix V and Arria V GZ devices using the 10G datapath Enable embedded reset control On Off This option is turned on by default When On the embedded reset controller initiates the reset sequence when it receives a positive edge on the phy_mgmt_clk_reset input signal Disable this option to implement your own reset sequence using the tx_analogreset rx_ a...

Page 257: ...ratix V Devices PLL Reconfiguration Parameters The following table describes the options available on the PLL Reconfiguration tab Note The PLL reconfiguration options are not available for the GT datapath Table 10 6 PLL Reconfigurations Name Value Description Allow PLL CDR Reconfiguration On Off You must enable this option if you plan to reconfigure the PLLs in your design This option is also requ...

Page 258: ...er to the Transceiver Clocking chapter in the device handbook for the device family you are using Number of reference clocks 1 5 Specifies the number of input reference clocks More than one reference clock may be required if your design reconfigures channels to run at multiple frequencies Main TX PLL logical index 0 3 Specifies the index for the TX PLL that should be instantiated at startup Logica...

Page 259: ...s increases in the following way Standard datapath The tx_parallel_data bus is 44 bits per lane however only the loworder number of bits specified by the FPGA fabric transceiver interface width contain valid data for each lane The rx_parallel_data bus is 64 bits per lane however only the loworder number of bits specified by the FPGA fabric transceiver interface width contain valid data 10G datapat...

Page 260: ...te phy_mgmt_read phy_mgmt_waitrequest pll_ref_clk tx_coreclkin n 1 0 rx_coreclkin n 1 0 Avalon MM PHY Management Interface Avalon STTX and RX to and from MAC Serial Data Dynamic Reconfiguration Reset Control and Status Optional Clocks Optional Note By default block diagram shown in the MegaWizard Plug In Manager labels the external pins with the interface type and places the interface name inside ...

Page 261: ...s RX parallel data driven by the Low Latency PHY IP Core Data driven from this interface is always valid rx_clkout n 1 0 Output Low speed clock recovered from the serial data rx_ready n 1 0 Output This is the ready signal for the RX interface The ready latency on this interface is 0 so that the MAC must be able to accept data as soon as the PMA comes out of reset This signal is available if you se...

Page 262: ...that the TX PLL is locked to the input reference clock This signal is asynchronous tx_bitslip n 1 0 Input When set the data sent to the PMA is slipped The maximum number of bits that can be slipped is equal to the value selected in the serialization factor field 1 or d 1 rx_bitslip n 1 0 Input When set the RX word aligner operates in bit slip mode Low Latency PHY Clock Interface The following tabl...

Page 263: ...ded PCS Channels for a SDC constraint you must include in your design tx_analogreset n 1 0 Input When asserted resets all blocks in the TX PMA tx_cal_busy n 1 0 Output When asserted indicates that the initial TX calibration is in progress It is also asserted if reconfiguration controller is reset It will not be asserted if you manually re trigger the calibration IP You must hold the channel in res...

Page 264: ...Serial Data Rx Serial Data n n The following table describes the signals in the PHY Management interface Table 10 12 Avalon MM PHY Management Interface Signal Name Direction Description phy_mgmt_clk Input Avalon MM clock input There is no frequency restriction for the phy_mgmt_clk however if you plan to use the same clock for the PHY management interface and transceiver reconfiguration you must re...

Page 265: ...may have undefined side effects Table 10 13 Low Latency PHY IP Core Registers Part 1 of 2 Word Addr Bits R W Register Name Description Reset Control Registers Automatic Reset Controller 0x041 31 0 RW reset_ch_bitmask Reset controller channel bitmask for digital resets The default value is all 1s Channel n can be reset when bit n 1 0x042 1 0 W reset_control write Writing a 1 to bit 0 initiates a TX...

Page 266: ...nfiguration interface compensates for variations due to PVT Each channel and each TX PLL have separate dynamic reconfiguration interfaces The MegaWizard Plug In Manager provides informational messages on the connectivity of these interfaces The following example shows the messages for a single duplex channel Example 10 1 Informational Messages for the Transceiver Reconfiguration Interface PHY IP w...

Page 267: ...lowing example to remove this restriction This example redefines the pma_bonding_master parameter using the Quartus II Assignment Editor In this example the pma_bonding_master was originally assigned to physical channel 1 The original assignment could also have been to physical channel 4 The to parameter reassigns the pma_bonding_master to the Low Latency PHY instance name You must substitute the ...

Page 268: ... Simulation Testbench for a description of the directories and files that the Quartus II software creates automatically when you generate your Low Latency PHY IP Core Refer to the Altera wiki for an example testbench that you can use as a starting point in creating your own verification environment UG 01080 2015 01 19 Simulation Files and Example Testbench 10 21 Low Latency PHY IP Core Altera Corp...

Page 269: ...l interfaces and modules of the Deterministic Latency PHY IP Core As the figure shows the physical coding sublayer PCS includes the following functions TX and RX Phase Compensation FIFO Byte serializer and deserializer 8B 10B encoder and decoder Word aligner TX bit slipper 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logo...

Page 270: ...gure transceiver settings Finally the PMA transmits and receives serial data Related Information Implementing the CPRI Protocol Using the Deterministic PHY IP Core Avalon Interface Specifications Deterministic Latency Auto Negotiation The Deterministic Latency PHY IP Core supports auto negotiation When required the channels initialize at the highest supported frequency and switch to successively l...

Page 271: ...on provides an overview of the calculation that help you achieve deterministic delay in the Deterministic Latency PHY IP core This figure illustrates the TX and RX channels when configured as a wireless basestation communicating to a remote radio head RRH using a CPRI or OBSAI interface The figure also provides an overview of the calculations that guarantee deterministic delay As this figure illus...

Page 272: ...se difference between the tx_clkout and rx_clkout and the clock output of the PLL as shown in above figure and ensure the delay through the FIFO to a certain accuracy Note Systems that require multiple frequencies in a single transceiver block must use a delay estimate FIFO to determine delay estimates and the required phase adjustments Deterministic Latency PHY Delay Estimation Logic This section...

Page 273: ... For REC For REC RX PCS latency in parallel clock cycles RX PMA latency in UI rx_clkout phase shift of tx_clkout TX_latency_REC TX PCS latency in parallel clock cycles TX PMA latency in UI RX_latency_REC Example 11 3 For Round Trip Delay Launch_time from TX pins clock arrival time data arrival time clock arr ival time TX latency in R E C tx bitslip 0 tPD G PLL to CM U PLL tfeedback TX _latency in ...

Page 274: ...ds on the location of the alignment pattern When the alignment pattern is in the upper symbol the delay is 0 5 cycles When the alignment pattern is in the lower symbol the delay is 1 0 cycles PCS Datapath Width RX Phase Comp FIFO Byte Ordering Deserial izer 8B 10B Word Aligner 10 9 Total RX Parallel Clock Cycles 9 10 Byte Serializer Deserializer Turned Off 8 bits 1 0 1 0 1 0 1 0 4 0 8 0 8 This lat...

Page 275: ... 62 Arria V 34 49 52 82 Stratix V 26 31 53 83 Deterministic Latency PHY Device Family Support This section describes Deterministic Latency PHY IP core device support IP cores provide either final or preliminary support for target Altera device families These terms have the following definitions Final support Verified with final timing models for this device Preliminary support Verified with prelim...

Page 276: ...ia V Cyclone V Stratix V Specifies the device family Arria V Cyclone V and Stratix V are available Mode of operation Duplex TX RX You can select to transmit data receive data or both Number of lanes 1 32 The total number of lanes in each direction FPGA fabric transceiver interface width 8 10 16 20 32 40 Specifies the word size between the FPGA fabric and PCS Refer to Table 11 7 for the data rates ...

Page 277: ... Data rate 4 Data rate 2 5 Data rate 2 Data rate 1 25 Data rate 1 This is the reference clock for the PHY PLL The available options are based on the Base data rate specified Enable tx_clkout feedback path for TX PLL On Off When On the core uses TX PLL feedback to align the TX core clock with the source to the TX PLL which is the RX recovered clock This configuration is shown in Using TX PLL Feedba...

Page 278: ...ab for the Deterministic Latency PHY IP core Name Value Description Word alignment mode The word aligner restores word boundaries of received data based on a predefined alignment pattern The word aligner automatically performs an initial alignment to the specified word pattern after reset deassertion You can select 1 of the following 2 modes Deterministic latency state machine or Manual 11 10 Addi...

Page 279: ... a word with a fixed latency of 3 cycles User logic can assume the LSB placement Altera recommends the deterministic latency state machine mode for new designs During the word alignment process the parallel clock shifts the phase to align to the data This phase shifting will be 2 10 cycles 20 in 10 bit mode 2 20 cycles 10 in 20 bit mode and 2 40 cycles 5 in 40 bit mode For double width datapaths u...

Page 280: ...us 0s or 1s This option also creates the rx_ rlv output signal which is asserted when a run length violation is detected Run length 5 160 Specifies the threshold for a run length violation Must be a multiple of 5 Create optional word aligner status ports On Off Enable this option to include the rx_patterndetect and rx_syncstatus ports Create optional 8B 10B control and status ports On Off Enable t...

Page 281: ...re This table lists the PLL Reconfiguration options For more information about transceiver reconfiguration registers refer to PLL Reconfiguration Table 11 8 PLL Reconfiguration Options Name Value Description Allow PLL CDR Reconfiguration On Off You must enable this option if you plan to reconfigure the PLLs in your design This option is also required to simulate PLL reconfiguration Number of TX PL...

Page 282: ...stantiated at startup Logical index 0 corresponds to input clock 0 and so on TX PLL 0 3 Refer to General Options for a detailed explanation of these parameters PLL Type CMU Specifies the PLL type Base data rate 1 Lane rate 2 Lane rate 4 Lane rate Specifies Base data rate Input clock frequency Variable Specifies the frequency of the PLL input reference clock The PLL must generate an output frequenc...

Page 283: ...s links to describe analog parameters for the Deterministic Latency PHY IP core The following links provide information to specify the analog options for your device Related Information Analog Settings for Arria V Devices on page 19 2 Analog Settings for Arria V GZ Devices on page 19 11 Analog Settings for Cyclone V Devices on page 19 26 Analog Settings for Stratix V Devices on page 19 34 Interfac...

Page 284: ...vr n 70 1 0 reconfig_from_xcvr n 46 1 0 Avalon STTx from MAC High Speed Serial I O Avalon MM PHY Management Interface Reference Clock Reset Control and Status Optional Optional Required TX and RX Status Avalon ST Rx to MAC Transceiver Reconfiguration The block diagram shown in the MegaWizard Plug In Manager labels the external pins with the interface type and places the interface name inside the b...

Page 285: ...atak n d s 1 0 Input Data and control indicator for the transmitted data When 0 indicates that tx_parallel_data is data when 1 indicates that tx_parallel_data is control Table 11 10 Signal Definitions for tx_parallel_data with and without 8B 10B Encoding The following table shows the signals within tx_parallel_data that correspond to data control and status signals TX Data Word Description Signal ...

Page 286: ...rce data When 0 indicates that rx_parallel_ data is data when 1 indicates that rx_ parallel_data is control Table 11 12 Signal Definitions for rx_parallel_data with and without 8B 10B Encoding This table shows the signals within rx_parallel_data that correspond to data control and status signals RX Data Word Description Signal Definitions with 8B 10B Enabled rx_parallel_data 7 0 RX data bus rx_par...

Page 287: ...n 0 Input Receiver differential serial input data tx_serial_data n 0 Output Transmitter differential serial output data Related Information Avalon Interface Specifications Clock Interface for Deterministic Latency PHY This section describes the clocks for the Deterministic Latency PHY IP core The following table describes clocks for the Deterministic Latency PHY The input reference clock pll_ref_c...

Page 288: ... slipped If no bits were slipped the output is 19 The default value of rx_bitslipboundaryselectout 4 0 before alignment is achieved is 5 b01111 in 3G mode and 5 b11111 in 6G mode Optional Status Signals tx_bitslipboundaryselect n 5 1 0 Input This signal is used for bit slip word alignment mode It selects the number of bits that the TX block must slip to achieve a deterministic latency rx_disperr n...

Page 289: ...nterfaces for Deterministic Latency PHY The following table describes the signals in the optional reset control and status interface These signals are available if you do not enable the embedded reset controller Table 11 16 Avalon ST RX Interface Signal Name Direction Description pll_powerdown n 1 0 Input When asserted resets the TX PLL tx_digitalreset n 1 0 Input When asserted reset all blocks in...

Page 290: ...egister Interface and Descriptions for Deterministic Latency PHY Describes the register interface and descriptions for the Deterministic Latency PHY IP core The Avalon MM PHY management interface provides access to the Deterministic Latency PHY PCS and PMA registers that control the TX and RX channels the PMA powerdown and PLL registers and loopback modes The following figure illustrates the role ...

Page 291: ...lon MM clock input There is no frequency restriction for Stratix V devices however if you plan to use the same clock for the PHY management interface and transceiver reconfiguration you must restrict the frequency range of phy_mgmt_clk to 100 150 MHz to meet the specification for the transceiver reconfiguration clock phy_mgmt_clk_reset Input Global reset signal This signal is active high and level...

Page 292: ... n 0x022 31 0 R pma_tx_pll_is_locked Bit P indicates that the TX CMU PLL P is locked to the input reference clock There is typically one pma_tx_pll_is_locked bit per system Reset Control Registers Automatic Reset Controller 0x041 31 0 RW reset_ch_bitmask Reset controller channel bitmask for digital resets The default value is all 1s Channel n can be reset when bit n 1 0x42 1 0 W reset_control writ...

Page 293: ...reset condition 1 RW reset_tx_digital Writing a 1 causes the internal TX digital reset signal to be asserted resetting all channels enabled in reset_ch_bitmask You must write a 0 to clear the reset condition PMA Control and Status Registers 0x061 31 0 RW phy _ serial _ loopback Writing a 1 to channel n puts channel n in serial loopback mode For information about pre or post CDR serial loopback mod...

Page 294: ...ryselect out This is an output from the bit slip word aligner which shows the number of bits slipped From block Word aligner 0 R Reserved 0x082 31 1 R pcs8g_tx_status Reserved 0 RW Reserved 0x083 31 6 RW pcs8g_tx_control Reserved 5 1 RW tx_bitslipboundary_ select Sets the number of bits that the TX bit slipper needs to slip To block Word aligner 0 RW tx_invpolarity When set the TX interface invert...

Page 295: ... connectivity of these interfaces The following example shows the messages for a single duplex channel Although you must initially create a separate reconfiguration interface for each channel and TX PLL in your design when the Quartus II software compiles your design it reduces the number of reconfiguration interfaces by merging reconfiguration interfaces The synthesized design typically includes ...

Page 296: ... Connectivity on page 16 56 Channel Placement and Utilization for Deterministic Latency PHY This section describes the channel placement utilization restrictions for the Deterministic Latency PHY IP core The Deterministic Latency PHY IP Core has the following restriction on channel placement Channels 1 and 2 in transceiver banks GXB_L0 and GXB_R0 of Arria V devices are not available for determinis...

Page 297: ... Ch 1 Ch 2 Ch 3 Ch 4 Ch 5 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 0 Ch 0 Ch 1 Ch 2 Ch 3 Ch 4 Ch 5 Not Available for Deterministic Protocols Not Available for Deterministic Protocols 1 1 Note 1 In ArriaV GZ devices channel 1 and 2 are available for deterministic latency protocols SDC Timing Constraints The SDC timing constraints and approaches to identify false paths listed for Stratix V Native PHY IP apply to...

Page 298: ...file requirements for the Deterministic Latency PHY IP core Refer to Running a Simulation Testbench for a description of the directories and files that the Quartus II software creates automatically when you generate your Deterministic Latency PHY IP Core Related Information Running a Simulation Testbench 11 30 Simulation Files and Example Testbench for Deterministic Latency PHY UG 01080 2015 01 19...

Page 299: ...ive PHY IP Core As this figure illustrates TX PLL and clock data recovery CDR reference clocks from the pins of the device are input to the PLL module and CDR logic When enabled the 10G or Standard PCS drives TX parallel data and receives RX parallel data When neither PCS is enabled the Native PHY operates in PMA Direct mode 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION...

Page 300: ...ibration and dynamic reconfiguration of the PLLs You specify the initial configuration when you parameterize the IP core The Transceiver Native PHY IP Core connects to the Transceiver Reconfiguration Controller IP Core to dynamically change reference clocks and PLL connectivity at runtime Device Family Support for Stratix V Native PHY This section describes the device family support available in t...

Page 301: ...ar protocol or application If you apply a preset the parameters with specific required values are set for you When applied the preset is in boldface and remains as such unless you change some of the preset parameters Selecting a preset does not prevent you from changing any parameter to meet the requirements of your design The following figure illustrates the Preset panel and form to create custom...

Page 302: ...e fastest 3_H3 Specifies the speed grade Message level for rule violations error warning When you select the error message level the Quartus II rules checker reports an error if you specify incompatible parameters If you select the warning message level the Quartus II rules checker reports a warning instead of an error Datapath Options Enable TX datapath On Off When you turn this option On the cor...

Page 303: ...n of the transceiver Select fb_compensation feedback compensation to use the same clock source for multiple channels across different transceiver banks to reduce clock skew For more information about bonding refer to Bonded Channel Configurations Using the PLL Feedback Compensation Path in volume 2 of the Stratix V Device Handbook Enable simplified data interface On Off When you turn this option O...

Page 304: ...to generate the correct frequencies for the parallel and serial clocks TX PLL base data rate Device Dependent Specifies the base data rate for the clock input to the TX PLL Select a base data rate that minimizes the number of PLLs required to generate all the clocks required for data transmission By selecting an appropriate base data rate you can change data rates by changing the divider used by t...

Page 305: ... 1 0 port of the Stratix Native PHY Use the Stratix V Transceiver PLL IP Core to instantiate a CMU or ATX PLL Use Altera Phase Locked Loop ALTERA_ PLL Megafunction to instantiate a fractional PLL Number of TX PLLs 1 4 Specifies the number of TX PLLs that can be used to dynamically reconfigure channels to run at multiple data rates If your design does not require transceiver TX PLL dynamic reconfig...

Page 306: ...r data transmission By selecting an appropriate PLL base data rate you can change data rates by changing the TX local clock division factor used by the clock generation block Reference clock frequency Device Dependent Specifies the frequency of the reference clock for the Selected reference clock source index you specify You can define a single frequency for each PLL You can use the Transceiver Re...

Page 307: ...red clock Enable rx_is_lockedtodata port On Off When you turn this option On the rx_is_lockedto data port is an output of the PMA Enable rx_is_lockedtoref port On Off When you turn this option On the rx_is_ lockedtoref port is an output of the PMA Enable rx_set_locktodata and rx_set_locktoref ports On Off When you turn this option On the rx_set_ locktodata and rx_set_locktoref ports are outputs of...

Page 308: ... receiver detect block initiates the detection process Enable tx_pma_rxfound port QPI Off When you turn this option On the core includes tx_ pma_rxfound output status port This port is only used for QPI applications The RX detect block in the TX PMA detects the presence of a receiver at the other end of the channel tx_pma_rxfound indicates the result of detection Enable rx_pma_qpipulldn port QPI O...

Page 309: ...bit of a word for the RX deserializer for the PMA Direct datapath For example for an 8 bit interface width the latencies in UI are 11 for bit 7 12 for bit 6 13 for bit 5 and so on Table 12 8 Latency for RX Deserialization in Stratix V Devices FPGA Fabric Interface Width Stratix V Latency in UI 8 bits 11 10 bits 13 16 bits 19 20 bits 23 32 bits 35 40 bits 43 64 bits 99 80 bits 123 Table 12 9 Latenc...

Page 310: ...ts on the bus are 17 10 and 7 0 of the 80 bit bus The non active bits are tied to ground Table 12 10 Active Bits for Each Fabric Interface Width in PMA Direct Mode FPGA Fabric Interface Width Bus Bits Used 8 bits 7 0 10 bits 9 0 16 bits 17 10 7 0 20 bits 19 0 32 bits 37 30 27 20 17 10 7 0 40 bits 39 0 64 bits 77 70 67 60 57 50 47 40 37 30 27 20 17 10 7 0 80 bits 79 0 Related Information Transceive...

Page 311: ...coder Rate Match FIFO Deskew FIFO 8B 10B Encoder TX Bit Slip Word Aligner Parallel Clock Recovered Serializer Deserializer CDR tx_serial_data rx_serial_data rx_coreclkin tx_coreclkin Input Reference Clock from dedicated reference clock pin or fPLL Clock Divider Parallel and Serial Clocks Serial Clock Central Local Clock Divider Parallel Clock Serial Clock Parallel and Serial Clocks CMU ATX fPLL PL...

Page 312: ...ent srio_2p1 select this mode if you intend to implement the Serial RapidIO protocol Standard PCS PMA interface width 8 10 16 20 32 40 64 80 Specifies the width of the datapath that connects the FPGA fabric to the PMA The transceiver interface width depends upon whether you enable 8B 10B To simplify connectivity between the FPGA fabric and PMA the bus bits used are not contiguous for 16 and 32 bit...

Page 313: ...re deterministic latency such as CPRI Enable tx_std_pcfifo_full port On Off When you turn this option On the TX Phase compensation FIFO outputs a FIFO full status flag Enable tx_std_pcfifo_empty port On Off When you turn this option On the TX Phase compensation FIFO outputs a FIFO empty status flag Enable rx_std_pcfifo_full port On Off When you turn this option On the RX Phase compensation FIFO ou...

Page 314: ... should search for When the PMA is 16 or 20 bits wide the byte ordering block can optionally search for 1 or 2 symbols Byte order pattern hex User specified 8 10 bit pattern Specifies the search pattern for the byte ordering block Byte order pad value hex User specified 8 10 bit pattern Specifies the pad pattern that is inserted by the byte ordering block This value is inserted when the byte order...

Page 315: ...ncy and accommodate a wider range of FPGA interface widths The following table describes the byte serialization and deserialization options you can specify Table 12 13 Byte Serializer and Deserializer Parameters Parameter Range Description Enable TX byte serializer On Off When you turn this option On the PCS includes a TX byte serializer which allows the PCS to run at a lower clock frequency to ac...

Page 316: ...ttern hex User specified 20 bit pattern Specifies the ve positive disparity value for the RX rate match FIFO as a hexadecimal string RX rate match insert delete ve pattern hex User specified 20 bit pattern Specifies the ve negative disparity value for the RX rate match FIFO as a hexadecimal string Enable rx_std_rm_fifo_empty port On Off When you turn this option On the rate match FIFO outputs a FI...

Page 317: ... two bytes K28 5 D2 2 of C2 ordered sets during auto negotiation However the insertion or deletion of the first two bytes of C2 ordered sets can cause the auto negotiation link to fail For more information visit Altera Knowledge Base Support Solution Table 12 16 Status Flag Mappings for Simplified Native PHY Interface Status Condition Protocol Mapping of Status Flags to RX Data Value Full PHY IP C...

Page 318: ...D PAD OR EDB empty 11 Insertion Basic double width Serial RapidIO double width RXD 62 62 rx_ rmfifostatus 1 0 or RXD 46 45 rx_rmfifos tatus 1 0 or RXD 30 29 rx_ rmfifostatus 1 0 or RXD 14 13 rx_rmfifos tatus 1 0 2 b10 All other protocols Depending on the FPGA fabric to PCS interface width either RXD 46 45 rx_rmfifos tatus 1 0 or RXD 14 13 rx_rmfifos tatus 1 0 2 b10 11 PAD and EBD are control chara...

Page 319: ...es in bit slip mode the word aligner slips a single bit for every rising edge of the bit slip control signal The following table describes the word aligner and bit slip parameters Table 12 17 Word Aligner and Bit Slip Parameters Parameter Range Description Enable TX bit slip On Off When you turn this option On the PCS includes the bit slip function The outgoing TX data can be slipped by the number...

Page 320: ...0 32 Specifies the length of the pattern the word aligner uses for alignment RX word aligner pattern hex User specified Specifies the word aligner pattern in hex Number of word alignment patterns to achieve sync 1 256 Specifies the number of valid word alignment patterns that must be received before the word aligner achieves synchronization lock The default is 3 Number of invalid words to lose syn...

Page 321: ... bit reversal On Off When you turn this option On the word aligner reverses TX parallel data before transmitting it to the PMA for serialization You can only change this static setting using the Transceiver Reconfiguration Controller Enable RX bit reversal On Off When you turn this option On the rx_st_ bitrev_ena port controls bit reversal of the RX parallel data after it passes from the PMA to th...

Page 322: ...ously swapped during board layout Enable tx_std_elecidle port On Off When you turn this option On the tx_std_ elecidle input port is enabled When this signal is asserted it forces the transmitter to electrical idle This signal is required for the PCI Express protocol Enable rx_std_signaldetect port On Off When you turn this option On the optional tx_std_signaldetect output port is enabled This sig...

Page 323: ...es the PRBS patterns Table 12 19 Standard PCS PRBS Patterns PATTERN POLYNOMIAL PRBS 7 X7 X6 1 PRBS 8 X8 X7 X3 X2 1 PRBS 10 X10 X7 1 PRBS 15 X15 X14 1 PRBS 23 X23 X18 1 PRBS 31 X31 X28 1 The Standard PCS requires a specific word alignment for the PRBS pattern You must specify a word alignment pattern in the verifier that matches the generator pattern specified In the Standard PCS PRBS patterns avai...

Page 324: ... Word Aligner Size Word Aligner Pattern 8 bit PRBS 7 3 b010 3 b001 0x0000003040 PRBS 8 3 b000 3 b001 0x000000FF5A PRBS 23 3 b100 3 b001 0x0000003040 PRBS 15 3 b101 3 b001 0x0000007FFF PRBS 31 3 b110 3 b001 0x000000FFFF 10 bit PRBS 10 3 b000 3 b010 0x00000003FF PRBS 15 3 b101 3 b000 0x0000000000 PRBS 31 3 b110 3 b010 0x00000003FF 16 bit PRBS 7 3 b000 3 b010 0x0000003040 PRBS 23 3 b001 3 b101 0x0000...

Page 325: ...he transmitter When set to 1 b0 enables the PRBS generator 0xA0 5 R W PRBS RX Enable When set to 1 b1 enables the PRBS verifier in the receiver 4 R W PRBS Error Clear When set to 1 b1 deasserts rx_prbs_ done and restarts the PRBS pattern 0xA1 15 14 R W Sync badcg Must be set to 2 b00 to enable the PRBS verifier 13 R W Enable Comma Detect Must be set to 1 b0 to enable the PRBS verifier 11 R W Enabl...

Page 326: ...Byte Align Disable Auto aligns the bytes Must be set to 1 b0 to enable the PRBS verifier 0xB8 13 R W DW Sync State Machine Enable Enables the double width state machine Must be set to 1 b0 to enable the PRBS verifier 0xB9 11 R W Deterministic Latency State Machine Enable Enables a deterministic latency state machine Must be set to 1 b0 to enable the PRBS verifier 0xB A 11 R W Clock Power Down RX W...

Page 327: ...zer Frame Sync Disparity Generator TX Gear Box RX Gear Box Serializer Deserializer CDR tx_serial_data rx_serial_data rx_coreclkin tx_coreclkin Input Reference Clock From Dedicated Input Reference Clock Pin BER Monitor Clock Divider Parallel and Serial Clocks Serial Clock Central Local Clock Divider Parallel Clock Serial Clock Parallel and Serial Clocks CMU PLL ATX PLL fPLL tx_clkout rx_clkout PRBS...

Page 328: ... protocol with the 1588 precision time stamping feature teng_sdi 10G SDI 10G PCS PMA interface width 32 40 64 Specifies the width of the datapath that connects the FPGA fabric to the PMA FPGA fabric 10G PCS interface width 32 40 50 64 66 67 Specifies the FPGA fabric to TX PCS interface width The 66 bit FPGA fabric PCS interface width is achieved using 64 bits from the TX and RX parallel data and t...

Page 329: ... FIFO full threshold 0 31 Specifies the full threshold for the 10G PCS TX FIFO The active high TX FIFO full flag is synchronous to coreclk The default value is 31 TX FIFO empty threshold 0 31 Specifies the empty threshold for the 10G PCS TX FIFO The active high TX FIFO empty flag is synchronous to coreclk The default value is 0 TX FIFO partially full threshold 0 31 Specifies the partially full thr...

Page 330: ...s the active high tx_10g_ fifo_del port This signal is asserted when a word is deleted from the TX FIFO This signal is only used for the 10GBASE R protocol Enable tx_10g_fifo_insert port 10GBASE R On Off When you turn this option On the 10G PCS includes the active high tx_10g_ fifo_insert port This signal is asserted when a word is inserted into the TX FIFO This signal is only used for the 10GBASE...

Page 331: ... the clock phase difference between the PLD clock coreclkin and rxclkout register The TX FIFO is bypassed rx_data and rx_data_valid are registered at the FIFO output RX FIFO full threshold 0 31 Specifies the full threshold for the 10G PCS RX FIFO The default value is 31 RX FIFO empty threshold 0 31 Specifies the empty threshold for the 10G PCS RX FIFO The default value is 0 RX FIFO partially full ...

Page 332: ...rt rx_10g_fifo_full is synchronous to rx_clkout Enable rx_10g_fifo_pfull port On Off When you turn this option On the 10G PCS includes the active high rx_10g_ fifo_pfull port rx_10g_fifo_pfull is synchronous to rx_clkout Enable rx_10g_fifo_empty port On Off When you turn this option On the 10G PCS includes the active high rx_10g_ fifo_empty port Enable rx_10g_fifo_pempty port On Off When you turn ...

Page 333: ...e FIFO resets and begins searching for a new alignment pattern This signal is only available for the Interlaken protocol Enable rx_10g_fifo_align_en port Interlaken On Off When you turn this option On the 10G PCS includes the rx_10g_fifo_align_ en input port This signal is used for FIFO deskew for Interlaken When asserted the corresponding channel is enabled for alignment This signal is only avail...

Page 334: ...r data reads from the TX FIFO The value of this signal is latched once at the beginning of each Metaframe It controls whether data is read from the TX FIFO or SKIP Words are inserted for the current Metaframe It must be held static for 5 cycles before and 5 cycles after the tx_frame pulse When tx_10g_frame_burst_en is 0 the frame generator does not read data from the TX FIFO for current Metaframe ...

Page 335: ...rol word errors This signal remains asserted during the loss of block_lock and does not update until block_lock is recovered Enable rx_10g_frame_skip_ins port On Off When you turn this option On the 10G PCS includes the rx_10g_frame_skip_ ins output port This signal is asserted to indicate a SKIP word was received by the frame sync in a non SKIP word location within the metaframe Enable rx_10g_fra...

Page 336: ...bes the CRC 32 parameters Table 12 28 Interlaken CRC32 Generator and Checker Parameters Parameter Range Description Enable Interlaken TX CRC32 Generator On Off When you turn this option On the TX 10G PCS datapath includes the CRC32 function Enable Interlaken RX CRC32 Generator On Off When you turn this option On the RX 10G PCS datapath includes the CRC32 function Enable rx_10g_crc32_err port On Of...

Page 337: ...n IEEE 802 3 2008 Clause 49 The 64b 66b encoder sub block receives data from the TX FIFO and encodes the 64 bit data and 8 bit control characters to the 66 bit data block required by the 10GBASE R protocol The transmit state machine in the 64b 66b encoder sub block checks the validity of the 64 bit data from the MAC layer and ensures proper block sequencing The 64b 66b decoder sub block converts t...

Page 338: ...datapath includes the scrambler function This option is available for the Interlaken and 10GBASE R protocols Enable rx_10g_descram_err port On Off When you turn this option On the 10G PCS includes the rx_10g_descram_err port Interlaken Disparity Generator and Checker The Disparity Generator monitors the data transmitted to ensure that the running disparity remains within a 96 bit bound It adds the...

Page 339: ...On the 10G PCS includes the rx_10G_blk_lock output port This signal is asserted to indicate the receiver has achieved block synchronization This option is available for the Interlaken 10GBASE R and other protocols that user the PCS lock state machine to achieve and monitor block synchronization Enable rx_10g_blk_sh_err port On Off When you turn this option On the 10G PCS includes the rx_10G_blk_sh...

Page 340: ...ata slips 1 bit for every positive edge of the rx_10g_bitslip input he maximum shift is pcswidth 1 bits so that if the PCS is 64 bits wide you can shift 0 63 bits PRBS Verifier You can use the PRBS pattern generators for verification or diagnostics The pattern generator blocks support the following patterns Pseudo random binary sequence PRBS Pseudo random pattern Square wave Table 12 35 PRBS Param...

Page 341: ... Name Description 0x12D 15 0 R W Seed A for PRP Bits 15 0 of seed A for the pseudo random pattern 0x12E 15 0 Bits 31 16 of seed A for the pseudo random pattern 0x12F 15 0 Bits 47 21 of seed A for the pseudo random pattern 0x130 9 0 Bits 57 48 of seed A for the pseudo random pattern 0x131 15 0 R W Seed B for PRP Bits 15 0 of seed B for the pseudo random pattern 0x132 15 0 Bits 31 16 of seed B for t...

Page 342: ...S pattern generator in the transmitter 1 R W TX Test Pattern Select Selects between the square wave or pseudo random pattern generator The following encodings are defined 1 b1 Square wave 1 b0 Pseudo random pattern or PRBS 0 R W Data Pattern Select Selects the data pattern for the pseudo random pattern The following encodings are defined 1 b1 Two Local Faults Two 32 bit ordered sets are XORd with ...

Page 343: ...odings are defined 1 b1 Square wave 1 b0 Pseudo random pattern or PRBS PRBS Pattern Generator To enable the PRBS pattern generator write 1 b1 to the RX PRBS Clock Enable and TX PRBS Clock Enable bits The following table shows the available PRBS patterns Table 12 37 10G PCS PRBS Patterns Pattern Polynomial PRBS 31 X31 x28 1 PRBS 9 X9 x5 1 PRBS 23 X23 x18 1 PRBS 7 X7 x6 1 Pseudo Random Pattern Gener...

Page 344: ...ard and 10G PCS datapaths If you use dynamic reconfiguration to change between the Standard and 10G PCS datapaths your top level HDL file includes the port for both the Standard and 10G PCS datapaths In addition the Native PHY allows you to enable ports even for disabled blocks to facilitate dynamic reconfiguration The Native PHY uses the following prefixes for port names Standard PCS ports tx_std...

Page 345: ...fig_to_xcvr n 70 1 0 reconfig_from_xcvr n 46 1 0 tx_cal_busy n 1 0 rx_cal_busy n 1 0 Reconfiguration Interface Ports Native PHY Common Interfaces ext_pll_clk p 1 0 Table 12 38 Native PHY Common Interfaces Name Direction Description Clock Inputs and Output Signals tx_pll_refclk r 1 0 Input The reference clock input to the TX PLL tx_pma_clkout n 1 0 Output TX parallel clock output from PMA rx_pma_cl...

Page 346: ...ensitive reset signal If your design includes bonded TX PCS channels refer to Timing Constraints for Reset Signals when Using Bonded PCS Channels for a SDC constraint you must include in your design rx_analogreset n 1 0 Input When asserted resets the RX CDR deserial izer Active high edge sensitive reset signal rx_digitalreset n 1 0 Input When asserted resets the digital components of the RX datapa...

Page 347: ...iza tions for various parameterizations rx_parallel_data n 64 1 0 Output PCS RX parallel data Used when you enable either the Standard or 10G datapath For the Standard datapath if you turn on Enable simplified data interface rx_parallel_ data includes only the data and control signals necessary for the current configura tion Dynamic reconfiguration of the interface is not supported For the 10G PCS...

Page 348: ...ions rx_pma_qpipulldn Input Control input port for Quick Path Intercon nect QPI applications This is an active high signal When asserted the receiver pulls the input signal in low state Use this port only for QPI applications TX and RX Serial Ports tx_serial_data n 1 0 Output TX differential serial output data rx_serial_data n 1 0 Input RX differential serial output data Control and Status Ports r...

Page 349: ...parallel clock could be extended by 2 unit intervals UI during the clock slip operation This is an optional control input signal Reconfig Interface Ports reconfig_to_xcvr n 70 1 0 Input Reconfiguration signals from the Transceiver Reconfiguration Controller n grows linearly with the number of reconfiguration interfaces reconfig_from_xcvr n 46 1 0 Output Reconfiguration signals to the Transceiver R...

Page 350: ... tx_parallel_data for Various FPGA Fabric to PCS Parameterizations The following table shows the valid 11 bit data words with and without the byte deserializer for single and double word FPGA fabric to PCS interface widths Configuration Bus Used Bits Single word data bus byte deserializer disabled 10 0 word 0 Single word data bus byte serializer enabled 32 22 10 0 words 0 and 2 Double word data bu...

Page 351: ... 42 Location of Valid Data Words for rx_parallel_data for Various FPGA Fabric to PCS Parameterizations The following table shows the valid 16 bit data words with and without the byte deserializer for single and double word FPGA fabric to PCS interface widths Configuration Bus Used Bits Single word data bus byte deserializer disabled 15 0 word 0 Single word data bus byte serializer enabled 47 32 15...

Page 352: ...le n 1 0 rx_std_signaldetect n 1 0 rx_std_byterev_ena n 1 0 Byte Serializer Deserializer rx_std_polinv n 1 0 tx_std_polinv n 1 0 Polarity Inversion Table 12 43 Standard PCS Interface Ports Name Dir Synchronous to tx_std_coreclkin rx_std_coreclkin Description Clocks tx_std_clkout n 1 0 Output TX Parallel clock output rx_std_clkout n 1 0 Output RX parallel clock output The CDR circuitry recovers RX ...

Page 353: ...to perform another byte ordering operation This signal is an synchronous input signal however it must be asserted for at least 1 cycle of rx_std_clkout rx_std_byteorder_flag n 1 0 Output Yes Byte ordering status flag When asserted indicates that the byte ordering block has performed a byte order operation This signal is asserted on the clock cycle in which byte ordering occurred This signal is syn...

Page 354: ... width mode In double width mode the FPGA data width is twice the PCS data width to allow the fabric to run at half the PCS frequency rx_std_rmfifo_full n 1 0 Output No Rate match FIFO full flag When asserted the rate match FIFO is full You must synchronize this signal This port is only used for XAUI GigE and Serial RapidIO in double width mode Word Aligner rx_std_bitrev_ena n 1 0 Input No When as...

Page 355: ...Architec ture in Arria V Devices rx_std_wa_a1a2size n 1 0 Input No Used for the SONET protocol Assert when the A1 and A2 framing bytes must be detected A1 and A2 are SONET backplane bytes and are only used when the PMA data width is 8 bits rx_std_bitslip n 1 0 Input No Used when word aligner mode is bitslip mode For every rising edge of the rx_std_ bitslip signal the word boundary is shifted by 1 ...

Page 356: ...r This signal must be driven low when not in use because it causes the TX PMA to enter electrical idle mode with the TX serial data signals in tristate mode rx_std_signaldetect n 1 0 Output No Signal threshold detect indicator When asserted it indicates that the signal present at the receiver input buffer is above the programmed signal detection threshold value You must synchronize this signal Rel...

Page 357: ...10g_pyld_ins n 1 0 rx_10g_frame_mfrm_err n 1 0 rx_10g_frame_sync_err n 1 0 rx_10g_scram_err n 1 0 rx_10g_frame_skip_ins n 1 0 rx_10g_frame_skip_err n 1 0 rx_10g_frame_diag_err n 1 0 rx_10g_frame_diag_status 2 n 1 0 rx_10g_blk_lock n 1 0 rx_10g_blk_sh_err n 1 0 rx_10g_bitslip n 1 0 tx_10g_bitslip 7 n 1 0 rx_10g_clr_errblk_count n 1 0 rx_10g_highber n 1 0 rx_10g_clr_highber_cnt n 1 0 PRBS rx_10g_prb...

Page 358: ...ivided by 33 or equivalently the RX PMA data rate divided by 66 It is typically used for ethernet applications that use 66b 64b decoding TX FIFO tx_10g_control 9 n 1 0 Input TX control signals for the Interlaken 10GBASE R and Basic protocols Synchronous to tx_10g_coreclk_in The following signals are defined Interlaken mode 8 Active high synchronous error insertion control bit 7 3 Not Used 12 60 10...

Page 359: ...1 indicates a control word 0 Sync Header 1 indicates 1 data word Basic mode 64 bit 50 bit 40 bit 32 bit word widths 8 0 Not used tx_10g_data_valid n 1 0 Input When asserted indicates if tx_data is valid Synchronous to tx_10g_coreclk_in Use of this signal depends upon the protocol you are implementing as follows 10G BASE R Tie to 1 b1 Interlaken Acts as control for FIFO write enable You should tie ...

Page 360: ...you must use a synchronizer tx_10g_fifo_del n 1 0 Output When asserted indicates that a word has been deleted from the rate match FIFO This signal is used for the 10GBASE R protocol This signal is synchronous to tx_ 10g_coreclkin tx_10g_fifo_insert n 1 0 Output When asserted indicates that a word has been inserted into the rate match FIFO This signal is used for the 10GBASE R protocol This signal ...

Page 361: ...ignal that indicates the Synchronization Word location within a metaframe 3 Active high synchronous status signal that indicates a non SKIP Word in the SKIP Word location within a metaframe 2 Inversion signal when asserted indicates that the polarity of the signal has been inverted 1 Synchronization header a 1 indicates control word 0 Synchronization header a 1 indicates data word 10GBASE R mode 9...

Page 362: ...l word 0 Synchronization header a 1 indicates data word Basic mode 67 bit mode without Block Sync 9 3 Not used 66 bit mode without Block Sync 9 2 Not used 1 Synchronization header a 1 indicates control word 0 Synchronization header a 1 indicates data word Basic mode 64 bit 50 bit 40 bit and 32 bit modes 9 0 Not used rx_10g_fifo_rd_en n 1 0 Input Active high read enable signal for RX FIFO Asserting...

Page 363: ...FO for alignment Synchronous to rx_ 10g_coreclkin rx_10g_align_val n 1 0 Output For the Interlaken protocol an active high indication that the alignment pattern has been found Synchronous to rx_10g_coreclkin Rx_10g_fifo_del n 1 0 Output When asserted indicates that a word has been deleted from the TX FIFO This signal is used for the 10GBASE R protocol This signal is pulse stretched you must use a ...

Page 364: ..._frame n 1 0 Output For the Interlaken protocol asserted to indicate the beginning of a new metaframe inside the frame synchronizer This signal is pulse stretched you must use a synchronizer This signal is pulse stretched you must use a synchronizer to synchronize with rx_10g_clkout rx_10g_frame_lock n 1 0 Output For the Interlaken protocol asserted to indicate that the frame synchronizer state ma...

Page 365: ... rx_10g_frame_skip_err n 1 0 Output For the Interlaken protocol asserted to indicate a Skip Control Word error was received in a Skip Control Word location within the metaframe This signal is sticky during the loss of block lock and does not update until block lock is re established This signal is pulse stretched you must use a synchronizer to synchronize with rx_10g_clkout rx_10g_frame_diag_ err ...

Page 366: ...Gearbox Slips one bit per rising edge pulse tx_10g_bitslip 7 n 1 0 Input TX bit slip is controlled by tx_bitslip port Shifts the number of bit location specified by tx_ bitslip The maximum shift is pcswidth 1 64b 66b rx_10g_clr_errblk_count n 1 0 Input For the 10GBASE R protocol asserted to clear the error block counter which counts the number of times the RX state machine enters the RX error stat...

Page 367: ...in 6 N Bonded Clocking The Native PHY supports bonded clocking in which a single TX PLL generates the clock that drives the transmitter for up to 27 contiguous channels Bonded configurations conserve PLLs and reduce channel to channel clock skew Bonded channels do not support dynamic reconfiguration of the transceiver When you specify 6 N bonding the transceiver channels that reside in the same ba...

Page 368: ...entral Clock Divider Ch3 Local Clock Divider Ch2 Local Clock Divider Ch1 Central Clock Divider Ch0 Local Clock Divider Ch5 Local Clock Divider Ch4 Central Clock Divider Ch3 Local Clock Divider Ch2 Local Clock Divider Ch1 Central Clock Divider Ch0 Local Clock Divider 12 70 6 N Bonded Clocking UG 01080 2015 01 19 Altera Corporation Stratix V Transceiver Native PHY IP Core Send Feedback ...

Page 369: ...r up to 13 contiguous channels above and below the TX PLL for a total of 27 bonded channels as the following figure illustrates UG 01080 2015 01 19 6 N Bonded Clocking 12 71 Stratix V Transceiver Native PHY IP Core Altera Corporation Send Feedback ...

Page 370: ... 4 ATX PLL 10 9 8 7 6 5 Transceiver Bank 3 4 3 2 1 1 Transceiver Bank 2 Up to 7 channels above below the ATX PLL Up to 13 channels above below the ATX PLL 12 72 6 N Bonded Clocking UG 01080 2015 01 19 Altera Corporation Stratix V Transceiver Native PHY IP Core Send Feedback ...

Page 371: ...able as an RX channel because the CMU PLL is not available to recover the clock from received data Consequently the using the CMU PLL creates a gap in the contiguous channels Related Information Stratix V Device Datasheet Transceiver Clocking in Stratix V Devices xN Non Bonded Clocking Non bonded clocking routes only the high speed serial clock from the TX PLL to the transmitter channels The local...

Page 372: ...registers 10g_tx_pcs SYNC_DATA_REG set_false_path through 10gtxbitslip to get_registers 10g_tx_pcs SYNC_DATA_REG set_false_path through 10grxbitslip to get_registers 10g_rx_pcs SYNC_DATA_REG set_false_path through 10grxclrbercount to get_registers 10g_rx_pcs SYNC_DATA_REG set_false_path through 10grxclrerrblkcnt to get_registers 10g_rx_pcs SYNC_DATA_REG set_false_path through 10grxprbserrclr to ge...

Page 373: ...formance is affected more by variations due to PVT These process variations result in analog voltages that can be offset from required ranges The calibration performed by the dynamic reconfiguration interface compensates for variations due to PVT For more information about transceiver reconfiguration refer to Chapter 16 Transceiver Reconfiguration Controller IP Core Example 12 4 Informational Mess...

Page 374: ...otation marks set_parameter name pma_bonding_master 1 to PHY IP instance name Simulation Support The Quartus II release provides simulation and compilation support for the Stratix V Native PHY IP Core Refer to Running a Simulation Testbench for a description of the directories and files that the Quartus II software creates automatically when you generate your Stratix V Transceiver Native PHY IP Co...

Page 375: ...he slew settings associated with your datarate The IBIS AMI slew rate figure is defined as the approximate transmitter 20 80 rise time The ps figure should not be considered quantitative and is an approximate label only The IBIS AMI models will allow you to simulate any slew rate setting for any datarate or protocol UG 01080 2015 01 19 Slew Rate Settings 12 77 Stratix V Transceiver Native PHY IP C...

Page 376: ...6 5536 Gbps As the following figure illustrates TX PLL and clock data recovery CDR reference clocks from the pins of the device are input to the PLL module and CDR logic When enabled the Standard PCS drives TX parallel data and receives RX parallel data In PMA Direct mode the PMA serializes TX data it receives from the fabric and drives RX data to the fabric 2015 Altera Corporation All rights rese...

Page 377: ...reconfiguration buses connect the external Transceiver Reconfiguration Controller for calibration and dynamic reconfiguration of the channel and PLLs You specify the initial configuration when you parameterize the IP core The Transceiver Native PHY IP Core connects to the Transceiver Reconfiguration Controller IP Core to dynamically change reference clocks PLL connectivity and the channel configur...

Page 378: ...Standard PCS The presets specify the parameters required to the protocol specified General Parameters This section lists the parameters available on the General Options tab Table 13 2 General and Datapath Options Name Range Description Device speed grade 3fastest 6_H6 Specifies the speed grade Message level for rule violations error warning Allows you to specify the message level as follows error ...

Page 379: ... On Off When you turn this option On the data interface provides only the relevant interface to the FPGA fabric for the selected configuration You can only use this option for static configurations When you turn this option Off the data interface provides the full physical interface to the fabric Select this option if you plan to use dynamic reconfiguration that includes changing the interface to ...

Page 380: ...te is computed from the TX local clock division factor multiplied by the data rate Select a PLL base data rate that minimizes the number of PLLs required to generate all the clocks for data transmission By selecting an appropriate PLL base data rate you can change data rates by changing the TX local clock division factor used by the clock generation block Related Information Transceiver Architectu...

Page 381: ...he number of TX PLLs that can be used to dynamically reconfigure channels to run at multiple data rates If your design does not require transceiver TX PLL dynamic reconfiguration set this value to 1 The number of actual physical PLLs that are implemented depends on the selected clock network Each channel can dynamically select between n PLLs where n is the number of PLLs specified for this paramet...

Page 382: ...ally change the reference clock input to the PLL Note that the list of frequencies updates dynamically when you change the Data rate The Input clock frequency drop down menu is populated with all valid frequencies derived as a function of the Data rate and Base data rate Selected reference clock source 0 4 You can define up to 5 reference clock sources for the PLLs in your core The Reference clock...

Page 383: ...is an output of the PMA Enable rx_is_lockedto data port On Off When you turn this option On the rx_is_lockedto data port is an output of the PMA Enable rx_is_lockedtoref port On Off When you turn this option On the rx_is_lockedtoref port is an output of the PMA Enable rx_set_lockedto data and rx_set_ locktoref ports On Off When you turn this option On the rx_set_lockedt data and rx_set_lockedtoref...

Page 384: ...cy in UI 8 bits 43 10 bits 53 16 bits 67 20 bits 83 64 bits 131 80 bits 163 The following table shows the bits used for all FPGA fabric to PMA interface widths Regardless of the FPGA Fabric Interface Width selected all 80 bits are exposed for the TX and RX parallel data ports However depending upon the interface width selected not all bits on the bus will be active The following table shows which ...

Page 385: ...individual blocks in the Standard PCS Figure 13 2 The Standard PCS Datapath Transmitter PCS Transmitter PMA Receiver PMA Receiver PCS FPGA Fabric Byte Ordering RX Phase Compensation FIFO Byte Deserializer 8B 10B Decoder Rate Match FIFO Word Aligner Deserializer CDR TX Phase Compensation FIFO Byte Serializer 8B 10B Encoder TX Bit Slip Serializer rx_serial_data tx_serial_data tx_parallel data rx_par...

Page 386: ...era recommends that you select the appropriate preset for the Ethernet protocol Standard PCS PMA interface width 8 10 16 20 Specifies the width of the datapath that connects the FPGA fabric to the PMA The transceiver interface width depends upon whether you enable 8B 10B To simplify connectivity between the FPGA fabric and PMA the bus bits used are not contiguous for 16 and 32bit buses Refer to Ac...

Page 387: ...the FIFO is replaced by registers to reduce the latency through the PCS Use this mode for protocols that require deterministic latency such as CPRI Enable tx_std_pcfifo_full port On Off When you turn this option On the TX Phase compensa tion FIFO outputs a FIFO full status flag Enable tx_std_pcfifo_ empty port On Off When you turn this option On the TX Phase compensa tion FIFO outputs a FIFO empty...

Page 388: ... Block Parameters Parameter Range Description Enable RX byte ordering On Off When you turn this option On the PCS includes the byte ordering block Byte ordering control mode manual auto Specifies the control mode for the byte ordering block The following modes are available Manual Allows you to control the byte ordering block Auto The word aligner automatically controls the byte ordering block onc...

Page 389: ... to manual Once byte ordering has occurred you must deassert and reassert this signal to perform another byte ordering operation This signal is an synchronous input signal however it must be asserted for at least 1 cycle of rx_std_ clkout Enable rx_std_ byteorder_flag port On Off Enables the optional rx_std_byteorder_flag status output port When asserted indicates that the byte ordering block has ...

Page 390: ... control identifier Note For more information refer to the 8B 10B Encoder and 8B 10B Decoder sections in the Transceiver Architecture in Arria V Devices Table 13 14 8B 10B Encoder and Decoder Parameters Parameter Range Description Enable TX 8B 10B encoder On Off When you turn this option On the PCS includes the 8B 10B encoder Enable TX 8B 10B disparity control On Off When you turn this option On t...

Page 391: ...as listed in the following table This table uses the following definitions Basic double width The Standard PCS protocol mode GUI option is set to basic The FPGA data width is twice the PCS data width to allow the fabric to run at half the PCS frequency SerialTM RapidIO double width You are implementing the Serial RapidIO protocol The FPGA data width is twice the PCS data width to allow the fabric ...

Page 392: ...PHY IP Core for PCI Express PIPE Basic double width RXD 62 62 rx_ rmfifostatus 1 0 or RXD 46 45 rx_rmfifos tatus 1 0 or RXD 30 29 rx_ rmfifostatus 1 0 or RXD 14 13 rx_rmfifos tatus 1 0 2 b10 AND PAD OR EDB empty 13 XAUI GigE Serial RapidIO double width rx_std_rm_fifo_empty 1 b1 empty All other protocols Depending on the FPGA fabric to PCS interface width either RXD 46 45 rx_rmfifos tatus 1 0 or RX...

Page 393: ... 1 0 or RXD 14 13 rx_rmfifos tatus 1 0 2 b01 All other protocols Depending on the FPGA fabric to PCS interface width either RXD 46 45 rx_rmfifos tatus 1 0 or RXD 14 13 rx_rmfifos tatus 1 0 2 b01 Related Information Transceiver Architecture in Arria V Devices Word Aligner and BitSlip Parameters The word aligner aligns the data coming from RX PMA deserializer to a given word boundary When the word a...

Page 394: ...d alignment You can only use this mode with 8B 10B encoding The data width at the word aligner can be 10 or 20 bits When you select this word aligner mode the synchronous state machine has hysteresis that is compatible with XAUI However when you select cpri for the Standard PCS Protocol Mode this option selects the deterministic latency word aligner mode Manual This mode enables word alignment by ...

Page 395: ...rnalign port On Off Enables the optional rx_std_wa_patternalign control input port Enable rx_std_wa_a1a2size port On Off Enables the optional rx_std_wa_a1a2size control input port Enable rx_std_bitslipboundarysel port On Off Enables the optional rx_std_wa_bitslipboun darysel status output port Enable rx_std_bitslip port On Off Enables the optional rx_std_wa_bitslip control input port Enable rx_std...

Page 396: ...ing of both 8 and10 bit words Enable TX polarity inversion On Off When you turn this option On the tx_ std_polinv port controls polarity inversion of TX parallel data before transmitting the parallel data to the PMA Enable RX polarity inversion On Off When you turn this option On asserting rx_std_polinv controls polarity inversion of RX parallel data after PMA transmission Enable rx_std_bitrev_ena...

Page 397: ...smitter to electrical idle Enable rx_std_signaldetect port On Off When you turn this option On the optional rx_std_signaldetect output port is enabled This signal is required for the PCI Express protocol If enabled the signal threshold detection circuitry senses whether the signal level present at the RX input buffer is above the signal detect threshold voltage that you specified For SATA SAS appl...

Page 398: ..._refclk r 1 0 tx_pma_clkout n 1 0 rx_pma_clkout n 1 0 rx_cdr_refclk r 1 0 Clock Input Output Signals rx_seriallpbken n 1 0 rx_setlocktodata n 1 0 rx_setlocktoref n 1 0 pll_locked p 1 0 rx_is_lockedtodata n 1 0 rx_is_lockedtoref n 1 0 rx_clkslip n 1 0 Control Status Ports pll_powerdown p 1 0 tx_analogreset n 1 0 tx_digitalreset n 1 0 rx_analogreset n 1 0 rx_digitalreset n 1 0 Resets QPI tx_pma_para...

Page 399: ...tantiate a fractional PLL which is external to the Native PHY IP then connect the output clock of this PLL to ext_pll_clk Resets pll_powerdown p 1 0 Input When asserted resets the TX PLL Active high edge sensitive reset signal By default the Arria V Native Transceiver PHY IP Core creates a separate pll_ powerdown signal for each logical PLL However the Fitter may merge the PLLs if they are in the ...

Page 400: ...bonded TX PCS channels refer to Timing Constraints for Reset Signals when Using Bonded PCS Channels for a SDC constraint you must include in your design rx_analogreset n 1 0 Input When asserted resets the RX CDR deserializer Active high edge sensitive asynchronous reset signal rx_digitalreset n 1 0 Input When asserted resets the digital components of the RX datapath Active high edge sensitive asyn...

Page 401: ...ktodata n 1 0 Input When asserted programs the RX CDR to manual lock to data mode in which you control the reset sequence using the rx_ set_locktoref and rx_set_ locktodata Refer to Transceiver Reset Sequence in Transceiver Reset Control in Arria V Devices for more information about manual control of the reset sequence rx_set_locktoref n 1 0 Input When asserted programs the RX CDR to manual lock t...

Page 402: ...early with the number of reconfiguration interfaces tx_cal_busy n 1 0 Output When asserted indicates that the initial TX calibration is in progress It is also asserted if reconfiguration controller is reset It will not be asserted if you manually re trigger the calibration IP You must hold the channel in reset until calibration completes rx_cal_busy n 1 0 Output When asserted indicates that the in...

Page 403: ...isabled 21 0 words 0 and 1 Double word data base bye serializer disabled 43 0 words 0 3 Table 13 22 Signal Definitions for rx_parallel_data with and without 8B 10B Encoding This table shows the signals within rx_parallel_data that correspond to data control and status signals RX Data Word Description Signal Definitions with 8B 10B Enabled rx_parallel_data 7 0 RX data bus rx_parallel_data 8 RX data...

Page 404: ...ble shows the valid 16 bit data words with and without the byte deserializer for single and double word FPGA fabric to PCS interface widths Configuration Bus Used Bits Single word data bus byte deserializer disabled 15 0 word 0 Single word data bus byte serializer enabled 47 32 15 0 words 0 and 2 Double word data base bye serializer disabled 31 0 words 0 and 1 Double word data base bye serializer ...

Page 405: ...dle n 1 0 rx_std_signaldetect n 1 0 rx_std_byterev_ena n 1 0 Byte Serializer Deserializer rx_std_polinv n 1 0 tx_std_polinv n 1 0 Polarity Inversion Table 13 24 Standard PCS Interface Ports Name Dir Synchronous to tx_std_coreclkin rx_std_coreclkin Description Clocks tx_std_clkout n 1 0 Output TX Parallel clock output rx_std_clkout n 1 0 Output RX parallel clock output The CDR circuitry recovers RX...

Page 406: ... to perform another byte ordering operation This signal is an synchronous input signal however it must be asserted for at least 1 cycle of rx_std_clkout rx_std_byteorder_flag n 1 0 Output Yes Byte ordering status flag When asserted indicates that the byte ordering block has performed a byte order operation This signal is asserted on the clock cycle in which byte ordering occurred This signal is sy...

Page 407: ...e width mode In double width mode the FPGA data width is twice the PCS data width to allow the fabric to run at half the PCS frequency rx_std_rmfifo_full n 1 0 Output No Rate match FIFO full flag When asserted the rate match FIFO is full You must synchronize this signal This port is only used for XAUI GigE and Serial RapidIO in double width mode Word Aligner rx_std_bitrev_ena n 1 0 Input No When a...

Page 408: ... Architec ture in Arria V Devices rx_std_wa_a1a2size n 1 0 Input No Used for the SONET protocol Assert when the A1 and A2 framing bytes must be detected A1 and A2 are SONET backplane bytes and are only used when the PMA data width is 8 bits rx_std_bitslip n 1 0 Input No Used when word aligner mode is bitslip mode For every rising edge of the rx_std_ bitslip signal the word boundary is shifted by 1...

Page 409: ...ect n 1 0 Output No Signal threshold detect indicator When asserted it indicates that the signal present at the receiver input buffer is above the programmed signal detection threshold value You must synchronize this signal Related Information Transceiver Architecture in Arria V Devices SDC Timing Constraints This section describes SDC timing constraints The Quartus II software reports timing viol...

Page 410: ... Inputs Example Apply 10ns max delay set_max_delay from tx_from_fifo to 8g pcs SYNC_DATA_REG1 10 You can use the set_false path command only during Timequest timing analysis Example 13 3 Using the set_false TimeQuest Constraint to Identify Asynchronous Inputs if TimeQuestInfo nameofexecutable eq quartus_fit else set_false_path from get_registers tx_from_fifo through txbursten to get_registers 8g_ ...

Page 411: ...quire 8 reconfiguration interfaces for connection to the external reconfiguration controller Reconfiguration interface offsets 0 3 are connected to the transceiver channels Reconfiguration interface offsets 4 7 are connected to the transmit PLLs Related Information Transceiver Architecture in Arria V Devices Simulation Support The Quartus II release provides simulation and compilation support for ...

Page 412: ...ery CDR reference clocks from the pins of the device are input to the PLL module and CDR logic When enabled the 10G or Standard PCS drives TX parallel data and receives RX parallel data When neither PCS is enabled the Native PHY operates in PMA Direct mode 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks ...

Page 413: ...ration and dynamic reconfiguration of the PLLs You specify the initial configuration when you parameterize the IP core The Transceiver Native PHY IP Core connects to the Transceiver Reconfiguration Controller IP Core to dynamically change reference clocks and PLL connectivity at runtime Device Family Support for Arria V GZ Native PHY This section describes the device family support available in th...

Page 414: ...r to meet the requirements of your design The following figure illustrates the Preset panel and form to create custom presets Figure 14 2 Preset Panel and Form To Create Custom Presets Parameterizing the Arria V GZ Native PHY This section provides a list of instructions on how to configure the Arria V GZ native PHY IP core Complete the following steps to configure the Arria V GZ Native PHY IP Core...

Page 415: ... the warning message level the Quartus II rules checker reports a warning instead of an error Datapath Options Enable TX datapath On Off When you turn this option On the core includes the TX datapath Enable RX datapath On Off When you turn this option On the core includes the RX datapath Enable Standard PCS On Off When you turn this option On the core includes the Standard PCS You can enable both ...

Page 416: ...iple channels across different transceiver banks to reduce clock skew For more information about bonding refer to Bonded Channel Configurations Using the PLL Feedback Compensation Path in Transceiver Clocking in Arria V devices chapter of the Arria V Device Handbook Enable simplified data interface On Off When you turn this option On the Native PHY presents only the relevant data bits When you tur...

Page 417: ... to generate the correct frequencies for the parallel and serial clocks TX PLL base data rate Device Dependent Specifies the base data rate for the clock input to the TX PLL Select a base data rate that minimizes the number of PLLs required to generate all the clocks required for data transmission By selecting an appropriate base data rate you can change data rates by changing the divider used by ...

Page 418: ...1 0 port of the Arria V GZ Native PHY Use the Arria V GZ Transceiver PLL IP Core to instantiate a CMU or ATX PLL Use Altera Phase Locked Loop ALTERA_ PLL Megafunction to instantiate a fractional PLL Number of TX PLLs 1 4 Specifies the number of TX PLLs that can be used to dynamically reconfigure channels to run at multiple data rates If your design does not require transceiver TX PLL dynamic recon...

Page 419: ...tor multiplied by the Data rate Select a PLL base data rate that minimizes the number of PLLs required to generate all the clocks for data transmission By selecting an appropriate PLL base data rate you can change data rates by changing the TX local clock division factor used by the clock generation block Reference clock frequency Device Dependent Specifies the frequency of the reference clock for...

Page 420: ...ency of the clock input to the CDR PPM detector threshold 1000 PPM Specifies the maximum PPM difference the CDR can tolerate between the input reference clock and the recovered clock Enable rx_pma_clkout port On Off When you turn this option On the RX parallel clock which is recovered from the serial received data is an output of the PMA Enable rx_is_lockedtodata port On Off When you turn this opt...

Page 421: ...ntrol input port This port is only used for QPI applications The RX detect block in the TX PMA detects the presence of a receiver at the other end of the channel After receiving a tx_pma_ txdetectrx request the receiver detect block initiates the detection process Enable tx_pma_rxfound port QPI On Off When you turn this option On the core includes tx_ pma_rxfound output status port This port is on...

Page 422: ...he RX channel The following table lists the best case latency for the most significant bit of a word for the RX deserializer for the PMA Direct datapath For example for an 8 bit interface width the latencies in UI are 11 for bit 7 12 for bit 6 13 for bit 5 and so on Table 14 8 Latency for RX Deserialization in Arria V GZ Devices FPGA Fabric Interface Width Arria V GZ Latency in UI 8 bits 11 10 bit...

Page 423: ...on For example if your interface is 16 bits the active bits on the bus are 17 0 and 7 0 of the 80 bit bus The non active bits are tied to ground Table 14 10 Active Bits for Each Fabric Interface Width FPGA Fabric Interface Width Bus Bits Used 8 bits 7 0 10 bits 9 0 16 bits 17 10 7 0 20 bits 19 0 32 bits 37 30 27 20 17 10 7 0 40 bits 39 0 64 bits 77 70 67 60 57 50 47 40 37 30 27 20 17 10 7 0 80 bit...

Page 424: ...coder Rate Match FIFO Deskew FIFO 8B 10B Encoder TX Bit Slip Word Aligner Parallel Clock Recovered Serializer Deserializer CDR tx_serial_data rx_serial_data rx_coreclkin tx_coreclkin Input Reference Clock from dedicated reference clock pin or fPLL Clock Divider Parallel and Serial Clocks Serial Clock Central Local Clock Divider Parallel Clock Serial Clock Parallel and Serial Clocks CMU ATX fPLL PL...

Page 425: ...ent srio_2p1 select this mode if you intend to implement the Serial RapidIO protocol Standard PCS PMA interface width 8 10 16 20 32 40 64 80 Specifies the width of the datapath that connects the FPGA fabric to the PMA The transceiver interface width depends upon whether you enable 8B 10B To simplify connectivity between the FPGA fabric and PMA the bus bits used are not contiguous for 16 and 32 bit...

Page 426: ...e deterministic latency such as CPRI Enable tx_std_pcfifo_full port On Off When you turn this option On the TX Phase compensation FIFO outputs a FIFO full status flag Enable tx_std_pcfifo_empty port On Off When you turn this option On the TX Phase compensation FIFO outputs a FIFO empty status flag Enable rx_std_pcfifo_full port On Off When you turn this option On the RX Phase compensation FIFO out...

Page 427: ...should search for When the PMA is 16 or 20 bits wide the byte ordering block can optionally search for 1 or 2 symbols Byte order pattern hex User specified 8 10 bit pattern Specifies the search pattern for the byte ordering block Byte order pad value hex User specified 8 10 bit pattern Specifies the pad pattern that is inserted by the byte ordering block This value is inserted when the byte order ...

Page 428: ...ncy and accommodate a wider range of FPGA interface widths The following table describes the byte serialization and deserialization options you can specify Table 14 13 Byte Serializer and Deserializer Parameters Parameter Range Description Enable TX byte serializer On Off When you turn this option On the PCS includes a TX byte serializer which allows the PCS to run at a lower clock frequency to ac...

Page 429: ...tern hex User specified 20 bit pattern Specifies the ve positive disparity value for the RX rate match FIFO as a hexadecimal string RX rate match insert delete ve pattern hex User specified 20 bit pattern Specifies the ve negative disparity value for the RX rate match FIFO as a hexadecimal string Enable rx_std_rm_fifo_empty port On Off When you turn this option On the rate match FIFO outputs a FIF...

Page 430: ... two bytes K28 5 D2 2 of C2 ordered sets during auto negotiation However the insertion or deletion of the first two bytes of C2 ordered sets can cause the auto negotiation link to fail For more information visit Altera Knowledge Base Support Solution Table 14 16 Status Flag Mappings for Simplified Native PHY Interface Status Condition Protocol Mapping of Status Flags to RX Data Value Full PHY IP C...

Page 431: ... PAD OR EDB empty 14 Insertion Basic double width Serial RapidIO double width RXD 62 62 rx_ rmfifostatus 1 0 or RXD 46 45 rx_rmfifos tatus 1 0 or RXD 30 29 rx_ rmfifostatus 1 0 or RXD 14 13 rx_rmfifos tatus 1 0 2 b10 All other protocols Depending on the FPGA fabric to PCS interface width either RXD 46 45 rx_rmfifos tatus 1 0 or RXD 14 13 rx_rmfifos tatus 1 0 2 b10 14 PAD and EBD are control charac...

Page 432: ...s in bit slip mode the word aligner slips a single bit for every rising edge of the bit slip control signal The following table describes the word aligner and bit slip parameters Table 14 17 Word Aligner and Bit Slip Parameters Parameter Range Description Enable TX bit slip On Off When you turn this option On the PCS includes the bit slip function The outgoing TX data can be slipped by the number ...

Page 433: ... 32 Specifies the length of the pattern the word aligner uses for alignment RX word aligner pattern hex User specified Specifies the word aligner pattern in hex Number of word alignment patterns to achieve sync 1 256 Specifies the number of valid word alignment patterns that must be received before the word aligner achieves synchronization lock The default is 3 Number of invalid words to lose sync...

Page 434: ... bit reversal On Off When you turn this option On the word aligner reverses TX parallel data before transmitting it to the PMA for serialization You can only change this static setting using the Transceiver Reconfiguration Controller Enable RX bit reversal On Off When you turn this option On the rx_st_ bitrev_ena port controls bit reversal of the RX parallel data after it passes from the PMA to th...

Page 435: ...usly swapped during board layout Enable tx_std_elecidle port On Off When you turn this option On the tx_std_ elecidle input port is enabled When this signal is asserted it forces the transmitter to electrical idle This signal is required for the PCI Express protocol Enable rx_std_signaldetect port On Off When you turn this option On the optional tx_std_signaldetect output port is enabled This sign...

Page 436: ...s the PRBS patterns Table 14 19 Standard PCS PRBS Patterns PATTERN POLYNOMIAL PRBS 7 X7 X6 1 PRBS 8 X8 X7 X3 X2 1 PRBS 10 X10 X7 1 PRBS 15 X15 X14 1 PRBS 23 X23 X18 1 PRBS 31 X31 X28 1 The Standard PCS requires a specific word alignment for the PRBS pattern You must specify a word alignment pattern in the verifier that matches the generator pattern specified In the Standard PCS PRBS patterns avail...

Page 437: ... Word Aligner Size Word Aligner Pattern 8 bit PRBS 7 3 b010 3 b001 0x0000003040 PRBS 8 3 b000 3 b001 0x000000FF5A PRBS 23 3 b100 3 b001 0x0000003040 PRBS 15 3 b101 3 b001 0x0000007FFF PRBS 31 3 b110 3 b001 0x000000FFFF 10 bit PRBS 10 3 b000 3 b010 0x00000003FF PRBS 15 3 b101 3 b000 0x0000000000 PRBS 31 3 b110 3 b010 0x00000003FF 16 bit PRBS 7 3 b000 3 b010 0x0000003040 PRBS 23 3 b001 3 b101 0x0000...

Page 438: ...he transmitter When set to 1 b0 enables the PRBS generator 0xA0 5 R W PRBS RX Enable When set to 1 b1 enables the PRBS verifier in the receiver 4 R W PRBS Error Clear When set to 1 b1 deasserts rx_prbs_ done and restarts the PRBS pattern 0xA1 15 14 R W Sync badcg Must be set to 2 b00 to enable the PRBS verifier 13 R W Enable Comma Detect Must be set to 1 b0 to enable the PRBS verifier 11 R W Enabl...

Page 439: ...Byte Align Disable Auto aligns the bytes Must be set to 1 b0 to enable the PRBS verifier 0xB8 13 R W DW Sync State Machine Enable Enables the double width state machine Must be set to 1 b0 to enable the PRBS verifier 0xB9 11 R W Deterministic Latency State Machine Enable Enables a deterministic latency state machine Must be set to 1 b0 to enable the PRBS verifier 0xB A 11 R W Clock Power Down RX W...

Page 440: ...mbler Descrambler Disparity Checker Block Synchronizer Frame Sync Disparity Generator TX Gear Box RX Gear Box Serializer Deserializer CDR tx_serial_data rx_serial_data rx_coreclkin tx_coreclkin Input Reference Clock From Dedicated Input Reference Clock Pin BER Monitor Clock Divider Parallel and Serial Clocks Serial Clock Central Local Clock Divider Parallel Clock Serial Clock Parallel and Serial C...

Page 441: ... SDI 10G PCS PMA interface width 32 40 64 Specifies the width of the datapath that connects the FPGA fabric to the PMA FPGA fabric 10G PCS interface width 32 40 50 64 66 67 Specifies the FPGA fabric to TX PCS interface width The 66 bit FPGA fabric PCS interface width is achieved using 64 bits from the TX and RX parallel data and the lower 2 bits from the control bus The 67 bit FPGA fabric PCS inte...

Page 442: ...FIFO full threshold 0 31 Specifies the full threshold for the 10G PCS TX FIFO The active high TX FIFO full flag is synchronous to coreclk The default value is 31 TX FIFO empty threshold 0 31 Specifies the empty threshold for the 10G PCS TX FIFO The active high TX FIFO empty flag is synchronous to coreclk The default value is 0 TX FIFO partially full threshold 0 31 Specifies the partially full thre...

Page 443: ... the active high tx_10g_ fifo_del port This signal is asserted when a word is deleted from the TX FIFO This signal is only used for the 10GBASE R protocol Enable tx_10g_fifo_insert port 10GBASE R On Off When you turn this option On the 10G PCS includes the active high tx_10g_ fifo_insert port This signal is asserted when a word is inserted into the TX FIFO This signal is only used for the 10GBASE ...

Page 444: ...de for 10GBASE R phase_comp This mode compensates for the clock phase difference between the PLD clock coreclkin and rxclkout register The TX FIFO is bypassed rx_data and rx_data_valid are registered at the FIFO output RX FIFO full threshold 0 31 Specifies the full threshold for the 10G PCS RX FIFO The default value is 31 RX FIFO empty threshold 0 31 Specifies the empty threshold for the 10G PCS R...

Page 445: ...nterlaken 10G PCS protocol mode is Basic and RX FIFO mode is phase_comp 10G PCS protocol mode is Basic and RX FIFO mode is register Enable rx_10g_fifo_full port On Off When you turn this option On the 10G PCS includes the active high rx_10g_ fifo_full port rx_10g_fifo_full is synchronous to rx_clkout Enable rx_10g_fifo_pfull port On Off When you turn this option On the 10G PCS includes the active ...

Page 446: ... You typically need this option when the fabric to PCS interface width is 66 Enable rx_10g_fifo_align_clr port Interlaken On Off When you turn this option On the 10G PCS includes the rx_10g_fifo_align_ clr input port When this signal is asserted the FIFO resets and begins searching for a new alignment pattern This signal is only available for the Interlaken protocol Enable rx_10g_fifo_align_en por...

Page 447: ...r the tx_frame pulse Enable tx_10g_frame_burst_en port On Off When you turn this option On the 10G PCS includes the tx_10g_frame_burst_ en input port This port controls frame generator data reads from the TX FIFO The value of this signal is latched once at the beginning of each Metaframe It controls whether data is read from the TX FIFO or SKIP Words are inserted for the current Metaframe It must ...

Page 448: ...m_ err output port This signal is asserted to indicate an metaframe error Enable rx_10g_frame_sync_err port On Off When you turn this option On the 10G PCS includes the rx_10g_frame_sync_ err output port This signal is asserted to indicate synchronization control word errors This signal remains asserted during the loss of block_lock and does not update until block_lock is recovered Enable rx_10g_f...

Page 449: ... message is inserted into the next Diagnostic Word generated by the frame generation block Interlaken CRC32 Generator and Checker CRC 32 provides a diagnostic tool on a per lane basis You can use CRC 32 to trace interface errors back to an individual lane The CRC 32 calculation covers the whole metaframe including the Diagnostic Word itself This CRC code value is stored in the CRC32 field of the D...

Page 450: ... Off When you turn this option On the 10G PCS includes the rx_10g_clr_errblk_ count input port When asserted error block counter that counts the number of RX errors resets to 0 This signal is only available for the 10GBASE R protocol 64b 66b Encoder and Decoder The 64b 66b encoder and decoder conform to the 10GBASE R protocol specification as described in IEEE 802 3 2008 Clause 49 The 64b 66b enco...

Page 451: ...G PCS datapath includes the scrambler function This option is available for the Interlaken and 10GBASE R protocols TX scrambler seed User specified 15 bit value You must provide a different seed for each lane This parameter is only required for the Interlaken protocol Enable RX scrambler On Off When you turn this option On the RX 10G PCS datapath includes the scrambler function This option is avai...

Page 452: ...GBASE R protocol specification as described in IEEE 802 3 2008 Clause 49 Table 14 33 Bit Reversal and Polarity Inversion Parameters Parameter Range Description Enable RX block synchronizer On Off When you turn this option On the 10G PCS includes the RX block synchron izer This option is available for the Interlaken and 10GBASE R protocols Enable rx_10g_blk_lock port On Off When you turn this optio...

Page 453: ...es in bitslip mode Enable tx_10g_bitslip port On Off When you turn this option On the 10G PCS includes the tx_10g_bitslip input port The data slips 1 bit for every positive edge of the tx_10g_bitslip input The maximum shift is pcswidth 1 bits so that if the PCS is 64 bits wide you can shift 0 63 bits Enable rx_10g_bitslip port On Off When you turn this option On the 10G PCS includes the rx_10g_bit...

Page 454: ...ier inverts the received pattern before verification You may need to invert the patterns if you connect to third party PRBS pattern generators and checkers Note Note All undefined register bits are reserved Table 14 36 Pattern Generator Registers Offset Bits R W Name Description 0x12D 15 0 R W Seed A for PRP Bits 15 0 of seed A for the pseudo random pattern 0x12E 15 0 Bits 31 16 of seed A for the ...

Page 455: ...S pattern generator in the transmitter 1 R W TX Test Pattern Select Selects between the square wave or pseudo random pattern generator The following encodings are defined 1 b1 Square wave 1 b0 Pseudo random pattern or PRBS 0 R W Data Pattern Select Selects the data pattern for the pseudo random pattern The following encodings are defined 1 b1 Two Local Faults Two 32 bit ordered sets are XORd with ...

Page 456: ...odings are defined 1 b1 Square wave 1 b0 Pseudo random pattern or PRBS PRBS Pattern Generator To enable the PRBS pattern generator write 1 b1 to the RX PRBS Clock Enable and TX PRBS Clock Enable bits The following table shows the available PRBS patterns Table 14 37 10G PCS PRBS Patterns Pattern Polynomial PRBS 31 X31 x28 1 PRBS 9 X9 x5 1 PRBS 23 X23 x18 1 PRBS 7 X7 x6 1 Pseudo Random Pattern Gener...

Page 457: ...G PCS datapaths If you use dynamic reconfiguration to change between the Standard and 10G PCS datapaths your top level HDL file includes the port for both the Standard and 10G PCS datapaths In addition the Native PHY allows you to enable ports even for disabled blocks to facilitate dynamic reconfiguration The Native PHY uses the following prefixes for port names Standard PCS ports tx_std_ rx_std_ ...

Page 458: ...econfig_to_xcvr n 70 1 0 reconfig_from_xcvr n 46 1 0 tx_cal_busy n 1 0 rx_cal_busy n 1 0 Reconfiguration Interface Ports Native PHY Common Interfaces ext_pll_clk p 1 0 Table 14 38 Native PHY Common Interfaces Name Direction Description Clock Inputs and Output Signals tx_pll_refclk r 1 0 Input The reference clock input to the TX PLL tx_pma_clkout n 1 0 Output TX parallel clock output from PMA rx_pm...

Page 459: ...ge sensitive reset signal If your design includes bonded TX PCS channels refer to Timing Constraints for Reset Signals when Using Bonded PCS Channels for a SDC constraint you must include in your design rx_analogreset n 1 0 Input When asserted resets the RX CDR deserializer Active high edge sensitive reset signal rx_digitalreset n 1 0 Input When asserted resets the digital components of the RX dat...

Page 460: ...d data interface rx_parallel_data includes only the data and control signals necessary for the current configuration Dynamic reconfiguration of the interface is not supported For the 10G PCS if the parallel data interface is less than 64 bits wide the low order bits of rx_parallel_data are valid For the 10G PCS operating in 66 40 mode the 66 bus is formed as follows rx_parallel_data 63 0 rx_ 10g_c...

Page 461: ...pback drives TX data to the RX interface rx_set_locktodata n 1 0 Input When asserted programs the RX CDR to manual lock to data mode in which you control the reset sequence using the rx_setlocktoref and rx_setlocktodata Refer to Reset Sequence for CDR in Manual Lock Mode in Transceiver Reset Control in Arria V GZ Devices for more information about manual control of the reset sequence rx_set_lockto...

Page 462: ...gress It is also asserted if reconfiguration controller is reset It will not be asserted if you manually re trigger the calibra tion IP You must hold the channel in reset until calibration completes rx_cal_busy n 1 0 Output When asserted indicates that the initial RX calibration is in progress It is also asserted if reconfiguration controller is reset It will not be asserted if you manually re tri...

Page 463: ...sabled 21 0 words 0 and 1 Double word data bus byte serializer enabled 43 0 words 0 3 Table 14 41 Signal Definitions for rx_parallel_data with and without 8B 10B Encoding This table shows the signals within rx_parallel_data that correspond to data control and status signals RX Data Word Description Signal Definitions with 8B 10B Enabled rx_parallel_data w 1 0 RX data bus w is the width you specify...

Page 464: ... 16 bit data words with and without the byte deserializer for single and double word FPGA fabric to PCS interface widths Configuration Bus Used Bits Single word data bus byte deserializer disabled 15 0 word 0 Single word data bus byte serializer enabled 47 32 15 0 words 0 and 2 Double word data bus byte serializer disabled 31 0 words 0 and 1 Double word data bus byte serializer enabled 63 0 words ...

Page 465: ...a n 1 0 rx_std_byteorder_flag n 1 0 rx_std_rmfifo_empty n 1 0 rx_std_rmfifo_full n 1 0 rx_std_polinv n 1 0 tx_std_polinv n 1 0 Table 14 43 Standard PCS Interface Ports Name Dir Synchro nous to tx_ std_ coreclkin rx_std_ coreclkin Description Clocks tx_std_clkout n 1 0 Output TX Parallel clock output rx_std_clkout n 1 0 Output RX parallel clock output The CDR circuitry recovers RX parallel clock fr...

Page 466: ... to perform another byte ordering operation This signal is an synchronous input signal however it must be asserted for at least 1 cycle of rx_std_clkout rx_std_byteorder_flag n 1 0 Output Yes Byte ordering status flag When asserted indicates that the byte ordering block has performed a byte order operation This signal is asserted on the clock cycle in which byte ordering occurred This signal is sy...

Page 467: ... empty This port is only used for XAUI GigE and Serial RapidIO in double width mode In double width mode the FPGA data width is twice the PCS data width to allow the fabric to run at half the PCS frequency rx_std_rmfifo_full n 1 0 Output No Rate match FIFO full flag When asserted the rate match FIFO is full You must synchronize this signal This port is only used for XAUI GigE and Serial RapidIO in...

Page 468: ...al mode you align words by asserting rx_st_wa_patternalign rx_st_wa_patternalign is edge sensitive For more information refer to the Word Aligner section in the Transceiver Architec ture in Arria V Devices rx_std_wa_a1a2size n 1 0 Input No Used for the SONET protocol Assert when the A1 and A2 framing bytes must be detected A1 and A2 are SONET backplane bytes and are only used when the PMA data wid...

Page 469: ...hold detect indicator When asserted it indicates that the signal present at the receiver input buffer is above the programmed signal detection threshold value You must synchronize this signal Related Information Transceiver Architecture in Arria V Devices 10G PCS Interface The following figure illustrates the top level signals of the 10G PCS If you enable both the 10G PCS and Standard PCS your top...

Page 470: ...ck n 1 0 rx_10g_pyld_ins n 1 0 rx_10g_frame_mfrm_err n 1 0 rx_10g_frame_sync_err n 1 0 rx_10g_scram_err n 1 0 rx_10g_frame_skip_ins n 1 0 rx_10g_frame_skip_err n 1 0 rx_10g_frame_diag_err n 1 0 rx_10g_frame_diag_status 2 n 1 0 rx_10g_blk_lock n 1 0 rx_10g_blk_sh_err n 1 0 rx_10g_bitslip n 1 0 tx_10g_bitslip 7 n 1 0 rx_10g_clr_errblk_count n 1 0 rx_10g_highber n 1 0 rx_10g_clr_highber_cnt n 1 0 PRB...

Page 471: ...0g_clk33out n 1 0 Output This clock is driven by the RX deserializer Its frequency is RX CDR PLL clock frequency divided by 33 or equivalently the RX PMA data rate divided by 66 It is typically used for ethernet applications that use 66b 64b decoding TX FIFO tx_10g_control 9 n 1 0 Input Yes TX control signals for the Interlaken 10GBASE R and Basic protocols Synchronous to tx_10g_ coreclk_in The fo...

Page 472: ...al for tx_data 39 32 3 MII control signal for tx_data 31 24 2 MII control signal for tx_data 23 16 1 MII control signal for tx_data 15 8 0 MII control signal for tx_data 7 0 Basic mode 67 bit word width 8 3 Not used 2 Inversion Bit must always be set to 1 b0 1 Sync Header 1 indicates a control word 0 Sync Header 1 indicates a data word Basic mode 66 bit word width 8 2 Not used 1 Sync Header 1 indi...

Page 473: ...e TX FIFO is full Synchronous to tx_std_clkout tx_10g_fifo_pfull n 1 0 Output Yes When asserted indicates that the TX FIFO is partially full tx_10g_fifo_empty n 1 0 Output No TX FIFO empty flag Synchronous to tx_std_ clkout This signal is pulse stretched you must use a synchronizer tx_10g_fifo_pempty n 1 0 Output No TX FIFO partially empty flag Synchronous to tx_ std_clkout This signal is pulse st...

Page 474: ...us signal that indicates the Synchronization Word location within a metaframe 3 Active high synchronous status signal that indicates a non SKIP Word in the SKIP Word location within a metaframe 2 Inversion signal when asserted indicates that the polarity of the signal has been inverted 1 Synchronization header a 1 indicates control word 0 Synchronization header a 1 indicates data word 10GBASE R mo...

Page 475: ...en Block Lock is achieved 8 Active high synchronous status signal that indicates a sync header error 7 2 Not used 1 Synchronization header a 1 indicates control word 0 Synchronization header a 1 indicates data word Basic mode 67 bit mode without Block Sync 9 3 Not used 66 bit mode without Block Sync 9 2 Not used 1 Synchronization header a 1 indicates control word 0 Synchronization header a 1 indic...

Page 476: ...IFO empty flag rx_10g_fifo_pempty n 1 0 Output Yes Active high RX FIFO partially empty flag rx_10g_fifo_align_clr n 1 0 Input Yes For the Interlaken protocol this signal clears the current word alignment when the RX FIFO acts as a deskew FIFO When it is asserted the RX FIFO is reset and searches for a new alignment pattern rx_10g_fifo_align_en n 1 0 Input Yes For the Interlaken protocol you must a...

Page 477: ...Generation Block The message must be held static for 5 cycles before and 5 cycles after the tx_frame pulse tx_10g_burst_en n 1 0 Input No For the Interlaken protocol controls frame generator reads from the TX FIFO Latched once at the beginning of each metaframe When 0 the frame generator inserts SKIPs When 1 the frame generator reads data from the TX FIFO Must be held static for 5 cycles before an...

Page 478: ...chron izer rx_10g_frame_sync_err n 1 0 Output No For the Interlaken protocol asserted to indicate a synchronization Control Word error was received in a synchronization Control Word location within the metaframe This signal is sticky if block lock is lost and does not update until block lock is re established This signal is pulse stretched you must use a synchron izer rx_10g_scram_err n 1 0 Output...

Page 479: ...ation is latched when a valid Diagnostic Word is received in a Diagnostic Word Metaframe location This signal is pulse stretched you must use a synchronizer Block Synchronizer rx_10g_blk_lock n 1 0 Output No Active high status signal that is asserted when block synchronizer acquires block lock Valid for the 10GBASE R and Interlaken protocols and any basic mode that uses the lock state machine to a...

Page 480: ...serted it remains high for at least 125 us rx_10g_clr_highber_ cnt n 1 0 Input No For the 10GBASE R protocol status signal asserted to clear the BER counter which counts the number of times the BER state machine enters the BER_BAD_SH state This signal has no effect on the operation of the BER state machine PRBS rx_10g_prbs_done Output When asserted indicates the verifier has aligned and captured c...

Page 481: ...egisters 10g_tx_pcs SYNC_DATA_REG set_false_path through 10gtxbitslip to get_registers 10g_tx_pcs SYNC_DATA_REG set_false_path through 10grxbitslip to get_registers 10g_rx_pcs SYNC_DATA_REG set_false_path through 10grxclrbercount to get_registers 10g_rx_pcs SYNC_DATA_REG set_false_path through 10grxclrerrblkcnt to get_registers 10g_rx_pcs SYNC_DATA_REG set_false_path through 10grxprbserrclr to get...

Page 482: ...ted more by variations due to process voltage and temperature PVT These process variations result in analog voltages that can be offset from required ranges The calibration performed by the dynamic reconfiguration interface compensates for variations due to PVT For more information about transceiver reconfiguration refer to Chapter 16 Transceiver Reconfiguration Controller IP Core Example 14 4 Inf...

Page 483: ... the pma_bonding_master was originally assigned to physical channel 1 The original assignment could also have been to physical channel 4 The to parameter reassigns the pma_bonding_master to the Deterministic Latency PHY instance name You must substitute the instance name from your design for the instance name shown in quotation marks set_parameter name pma_bonding_master 1 to PHY IP instance name ...

Page 484: ...k TX PLL Reference Clock CDR RX Serial Data to FPGA fabric Transceiver Reconfiguration Controller Reconfiguration to XCVR Reconfiguration from XCVR TX and RX Resets Calilbration Busy PLL and RX Locked Transceiver PHY Reset Controller TX Serial Data Serializer De Serializer Standard PCS 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX w...

Page 485: ...evice families These terms have the following definitions Final support Verified with final timing models for this device Preliminary support Verified with preliminary timing models for this device Table 15 1 Device Family Support Device Family Support Cyclone V devices Final Other device families No support Cyclone V Native PHY Performance and Resource Utilization Because the Standard PCS and PMA...

Page 486: ...ance with invalid parameters You must change incompatible parameter selections to proceed warning Quartus II checker will allow instance creation with invalid parameters but the instance will not compile successfully Datapath Options Enable TX datapath On Off When you turn this option On the core includes the TX datapath Enable RX datapath On Off When you turn this option On the core includes the ...

Page 487: ...interface provides only the relevant interface to the FPGA fabric for the selected configuration You can only use this option for static configurations When you turn this option Off the data interface provides the full physical interface to the fabric Select this option if you plan to use dynamic reconfiguration that includes changing the interface to the FPGA fabric Refer to Active Bits for Each ...

Page 488: ...selecting an appropriate PLL base data rate you can change data rates by changing the TX local clock division factor used by the clock generation block Related Information Transceiver Architecture in Cyclone V Devices Device Datasheet for Cyclone V Devices TX PMA Parameters Note For more information about PLLs in Cyclone V devices refer to the Cyclone V PLLs section in Clock Networks and PLLs in C...

Page 489: ... selected clock network Each channel can dynamically select between n PLLs where n is the number of PLLs specified for this parameter Note Refer to Transceiver Clocking in Cyclone V Devices chapter for more details Main TX PLL logical index 0 3 Specifies the index of the TX PLL used in the initial configuration Number of TX PLL reference clocks 1 5 Specifies the total number of reference clocks th...

Page 490: ...down menu is populated with all valid frequencies derived as a function of the Data rate and Base data rate Selected reference clock source 0 4 You can define up to 5 reference clock sources for the PLLs in your core The Reference clock frequency selected for index 0 is assigned to TX PLL 0 The Reference clock frequency selected for index 1 is assigned to TX PLL 1 and so on Selected clock network ...

Page 491: ...tput of the PMA Enable rx_is_lockedtoref port On Off When you turn this option On the rx_is_ lockedtoref port is an output of the PMA Enable rx_set_lockedtodata and rx_set_locktoref ports On Off When you turn this option On the rx_set_ lockedtdata and rx_set_lockedtoref ports are outputs of the PMA Enable rx_pma_bitslip_port On Off When you turn this option On the rx_pma_ bitslip is an input to th...

Page 492: ... TX Phase Compensation FIFO Byte Serializer 8B 10B Encoder TX Bit Slip Serializer rx_serial_data tx_serial_data tx_parallel data rx_parallel data 2 2 tx_coreclkin rx_coreclkin Recovered Clock from Master Channel Parallel Clock Serial Clock Serial Clock Parallel Clock tx_clkout rx_clkout Note For more information about the Standard PCS refer to the PCS Architecture section in the Transceiver Archit...

Page 493: ...2 5 Gbps Ethernet protocol Altera recommends that you select the appropriate preset for the Ethernet protocol Standard PCS PMA interface width 8 10 16 20 Specifies the width of the datapath that connects the FPGA fabric to the PMA The transceiver interface width depends upon whether you enable 8B 10B To simplify connectivity between the FPGA fabric and PMA the bus bits used are not contiguous for ...

Page 494: ..._latency register_fifo The following 2 modes are possible low_latency This mode adds 3 4 cycles of latency to the TX datapath register_fifo In this mode the FIFO is replaced by registers to reduce the latency through the PCS Use this mode for protocols that require deterministic latency such as CPRI RX FIFO mode low_latency register_fifo The following 2 modes are possible low_latency This mode add...

Page 495: ...byte ordering block realigns the data coming from the byte deserializer This block is necessary when the PCS to FPGA fabric interface width is greater than the PCS datapath Because the timing of the RX PCS reset logic is indeterminate the byte ordering at the output of the byte deserializer may or may not match the original byte ordering of the transmitted data Note For more information refer to t...

Page 496: ...attern in the most significant byte MSB of the byte deserialized data it inserts the appropriate number of user specified pad bytes to push the byte ordering pattern to the LSB position restoring proper byte ordering Enable rx_std_ byteorder_ena port On Off Enables the optional rx_std_byte_order_ena control input port When this signal is asserted the byte ordering block initiates a byte ordering o...

Page 497: ...s option On the PCS includes an RX byte deserializer which allows the PCS to run at a lower clock frequency to accommodate a wider range of FPGA interface widths Related Information Transceiver Architecture in Cyclone V Devices 8B 10B The 8B 10B encoder generates 10 bit code groups from the 8 bit data and 1 bit control identifier The 8B 10B decoder decodes the data into an 8 bit data and 1 bit con...

Page 498: ...he local system clock and the RX recovered clock RX rate match insert delete ve pattern hex User specified 20 bit pattern Specifies the ve positive disparity value for the RX rate match FIFO as a hexadecimal string RX rate match insert delete ve pattern hex User specified 20 bit pattern Specifies the ve negative disparity value for the RX rate match FIFO as a hexadecimal string When you enable the...

Page 499: ...r Simplified Native PHY Interface Status Condition Protocol Mapping of Status Flags to RX Data Value Full PHY IP Core for PCI Express PIPE Basic double width RXD 62 62 rx_ rmfifostatus 1 0 or RXD 46 45 rx_rmfifos tatus 1 0 or RXD 30 29 rx_ rmfifostatus 1 0 or RXD 14 13 rx_rmfifos tatus 1 0 2 b11 full XAUI GigE Serial RapidIO double width rx_std_rm_fifo_full 1 b1 full All other protocols Depending ...

Page 500: ... 2 b10 AND PAD OR EDB empty 15 Insertion Basic double width Serial RapidIO double width RXD 62 62 rx_ rmfifostatus 1 0 or RXD 46 45 rx_rmfifos tatus 1 0 or RXD 30 29 rx_ rmfifostatus 1 0 or RXD 14 13 rx_rmfifos tatus 1 0 2 b10 All other protocols Depending on the FPGA fabric to PCS interface width either RXD 46 45 rx_rmfifos tatus 1 0 or RXD 14 13 rx_rmfifos tatus 1 0 2 b10 15 PAD and EBD are cont...

Page 501: ...ligner operates in bitslip mode the word aligner slips a single bit for every rising edge of the bit slip control signal Note For more information refer to the Word Aligner section in the Transceiver Architecture inCycloneV Devices Table 15 14 Word Aligner and BitSlip Parameters Parameter Range Description Enable TX bit slip On Off When you turn this option On the PCS includes the bitslip function...

Page 502: ...h of the pattern the word aligner uses for alignment The pattern is specified in LSBtoMSB order RX word aligner pattern hex User specified Specifies the word aligner pattern in hex Number of word alignment patterns to achieve sync 1 256 Specifies the number of valid word alignment patterns that must be received before the word aligner achieves synchronization lock The default is 3 Number of invali...

Page 503: ...ors and to accommodate different layouts of data Table 15 15 Bit Reversal and Polarity Inversion Parameters Parameter Range Description Enable TX bit reversal On Off When you turn this option On the word aligner reverses TX parallel data before transmitting it to the PMA for serialization You can only change this static setting using the Transceiver Reconfiguration Controller Enable RX bit reversa...

Page 504: ...t control port swaps the order of the individual 8 or 10bit words received from the PMA Enable tx_std_polinv port On Off When you turn this option On the tx_ std_polinv input is enabled You can use this control port to swap the positive and negative signals of a serial differential link if they were erroneously swapped during board layout Enable rx_std_polinv port On Off When you turn this option ...

Page 505: ...OLTAGE VTT_OP55V set_instance_assignment name XCVR_RX_SD_OFF 1 set_instance_assignment name XCVR_RX_SD_ON 2 Interfaces The Native PHY includes several interfaces that are common to all parameterizations The Native PHY allows you to enable ports even for disabled blocks to facilitate dynamic reconfiguration The Native PHY uses the following prefixes for port names Standard PCS ports tx_std rx_std T...

Page 506: ...6 1 0 tx_cal_busy n 1 0 rx_cal_busy n 1 0 Reconfiguration Interface Ports Native PHY Common Interfaces ext_pll_clk p 1 0 Table 15 16 Native PHY Common Interfaces Name Direction Description Clock Inputs and Output Signals tx_pll_refclk r 1 0 Input The reference clock input to the TX PLL rx_pma_clkout n 1 0 Output RX parallel clock recovered clock output from PMA rx_cdr_refclk n 1 0 Input Input refe...

Page 507: ...et signal If your design includes bonded TX PCS channels refer to Timing Constraints for Reset Signals when Using Bonded PCS Channels for a SDC constraint you must include in your design rx_analogreset n 1 0 Input When asserted resets the RX CDR deserializer Active high edge sensitive asynchronous reset signal rx_digitalreset n 1 0 Input When asserted resets the digital components of the RX datapa...

Page 508: ...re informa tion about manual control of the reset sequence rx_set_locktoref n 1 0 Input When asserted programs the RX CDR to manual lock to reference mode in which you control the reset sequence using the rx_set_locktoref and rx_set_ locktodata Refer to Refer to Transceiver Reset Sequence in Transceiver Reset Control in CycloneV Devices for more information about manual control of the reset sequen...

Page 509: ...serted indicates that the initial TX calibration is in progress It is also asserted if reconfiguration controller is reset It will not be asserted if you manually re trigger the calibration IP You must hold the channel in reset until calibration completes rx_cal_busy n 1 0 Output When asserted indicates that the initial RX calibration is in progress It is also asserted if reconfiguration controlle...

Page 510: ...d 43 0 words 0 3 Table 15 19 Signal Definitions for rx_parallel_data with and without 8B 10B Encoding This table shows the signals within rx_parallel_data that correspond to data control and status signals RX Data Word Description Signal Definitions with 8B 10B Enabled rx_parallel_data 9 0 RX data bus rx_parallel_data 10 Synchronization status rx_parallel_data 11 Disparity error rx_parallel_data 1...

Page 511: ...ths Configuration Bus Used Bits Single word data bus byte deserializer disabled 15 0 word 0 Single word data bus byte serializer enabled 47 32 15 0 words 0 and 2 Double word data bus byte serializer disabled 31 0 words 0 and 1 Double word data bus byte serializer enabled 63 0 words 0 3 Related Information Timing Constraints for Bonded PCS and PMA Channels on page 17 10 Transceiver Architecture in ...

Page 512: ...ena n 1 0 Byte Serializer Deserializer rx_std_polinv n 1 0 tx_std_polinv n 1 0 Polarity Inversion Table 15 21 Standard PCS Interface Ports Name Dir Synchronous to tx_std_coreclkin rx_std_coreclkin Description Clocks tx_std_clkout n 1 0 Output TX Parallel clock output rx_std_clkout n 1 0 Output RX parallel clock output The CDR circuitry recovers RX parallel clock from the RX data stream tx_std_core...

Page 513: ...tes that the byte ordering block has performed a byte order operation This signal is asserted on the clock cycle in which byte ordering occurred This signal is synchronous to the rx_std_clkout clock You must a synchronizer this signal Byte Serializer and Deserializer rx_std_byterev_ena n 1 0 Input No This control signal is available in when the PMA width is 16 or 20 bits When asserted enables byte...

Page 514: ...icant bit first When enabled the receive circuitry receives all words in the reverse order The bit reversal circuitry operates on the output of the word aligner tx_std_bitslipboundar ysel 5 n 1 0 Input No BitSlip boundary selection signal Specifies the number of bits that the TX bit slipper must slip rx_std_bitslipboundar ysel 5 n 1 0 Output No This signal operates when the word aligner is in bits...

Page 515: ...y is shifted by 1 bit Each bitslip removes the earliest received bit from the received data You must synchronize this signal Miscellaneous tx_std_elecidle n 1 0 Input When asserted enables a circuit to detect a downstream receiver This signal must be driven low when not in use because it causes the TX PMA to enter electrical idle mode with the TX serial data signals in tristate mode rx_std_signald...

Page 516: ...eidleinfersel to get_registers SYNC_DATA_REG You can use the set_max_delay constraint on a given path to create a constraint for asynchronous signals that do not have a specific clock relationship but require a maximum path delay Example 15 2 Using the max_delay Constraint to Identify Asynchronous Inputs Example Apply 10ns max delay set_max_delay from tx_from_fifo to 8g pcs SYNC_DATA_REG1 10 You c...

Page 517: ...n interfaces for connection to the external reconfiguration controller Reconfiguration interface offsets 0 3 are connected to the transceiver channels Reconfiguration interface offsets 4 7 are connected to the transmit PLLs Related Information Transceiver Architecture in Cyclone V Devices Simulation Support The Quartus II release provides simulation and compilation support for the Native PHY IP Co...

Page 518: ...ualization DFE Yes Yes Adaptive equalization Yes Yes Loopback modes Pre CDR reverse serial loopback Yes Yes Yes Yes Post CDR reverse serial loopback Yes Yes Yes Yes PLL reconfigura tion Reference clock switching CDR ATX PLLs and TX PLLs Yes Yes Yes Yes TX PLL connected to a transceiver channel reconfiguration Yes Yes Yes Yes 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION...

Page 519: ...onfiguration in Arria V Devices and Dynamic Reconfiguration in Cyclone V Devices These chapters are included in the Stratix V Arria V and Cyclone V device handbooks respectively Related Information Dynamic Reconfiguration in Stratix V Devices Dynamic Reconfiguration in Arria V Devices Dynamic Reconfiguration in Cyclone V Devices Transceiver Reconfiguration Controller System Overview This section d...

Page 520: ...r n 0 Transceiver PHY Registers to reconfigure User Application Including MAC AlteraV Series FPGA S M Master M S MIF ROM An embedded controller programs the Transceiver Reconfiguration Controller using its Avalon MM slave interface The reconfig_to_xcvr and reconfig_from_xcvr buses include the Avalon MM address read write readdata writedata and signals that connect to features related to calibratio...

Page 521: ...s to the PCS datapath settings clock settings and PLL parameters You specify the mif using write commands on the Avalon MM PHY management interface After the streaming operation is specified the update proceeds in a single step For more information refer to Changing Transceiver Settings Using Streamer Based Reconfiguration In the direct write mode you perform Avalon MM reads and writes to initiate...

Page 522: ...ation 350 400 0 0 70 us channel ATX PLL calibration 650 450 0 4 60 us channel Analog Features EyeQ 300 200 0 0 AEQ 700 500 0 0 40 us channel Reconfiguration Features Channel and PLL reconfi guration 400 500 0 0 16 PLL reconfiguration only 250 350 0 0 Parameterizing the Transceiver Reconfiguration Controller IP Core Complete the following steps to configure the Transceiver Reconfiguration Controlle...

Page 523: ...ailable for Arria V and Cyclone V devices are a subset of those available for Stratix V devices Refer to Device Support for Dynamic Reconfiguration for more information about available functions Interface Bundles Number of reconfiguration interfaces IF Specifies the total number of reconfiguration interfaces that connect to the Transceiver Reconfiguration Controller There is one interface for each...

Page 524: ...l_busy and rx_cal_busy ports These signals are asserted when calibra tion is active Analog Features Enable Analog controls On Off When enabled TX and RX signal conditioning features are enabled Enable EyeQ block On Off When enabled you can use the EyeQ the on chip signal quality monitoring circuitry to estimate the actual eye opening at the receiver This feature is only available for Stratix V dev...

Page 525: ...egaWizard Plug In Manager labels the external pins with the interface type and places the interface name inside the box The interface type and name are used in the Hardware Component Description File _hw tcl If you click Show signals the block diagram expands to show all of the signals of the component given the options currently selected in the MegaWizard Plug In Manager For more information abou...

Page 526: ...econfiguration interface The Transceiver Reconfiguration Controller communicates with the PHY IP cores using this interface In the following table n is the number of reconfiguration interfaces connected to the Transceiver Reconfiguration Controller Table 16 6 Transceiver Reconfiguration Interface Signal Name Direction Description reconfig_to_xcvr n 70 1 0 Output Parallel reconfiguration bus from t...

Page 527: ...signal is asserted while initial RX calibra tion is in progress and no further reconfiguration operations should be performed It is also asserted if reconfiguration controller is reset It will not be asserted if you manually re trigger the calibration IP You can monitor this signal to determine the status of the Transceiver Reconfiguration Controller Reconfiguration Management Interface This secti...

Page 528: ...on if your design includes more than one Transceiver Reconfiguration Controllers on the same side of the FPGA they all must share the mgmt_clk_clk signal Note The frequency range depends on the device speed grade Slower speed grade variants of Stratix V and Arria V GZ devices may require a 100 MHz reconfiguration clock to close timing mgmt_rst_reset Input This signal resets the Transceiver Reconfi...

Page 529: ...econfiguration Controller Registers Direct Addressing Address Offset 0x00 0x13 0x0B 0x1B 0x2B 0x33 0x3B 0x43 0x48 0x7F Transceiver Reconfiguration Controller Avalon MM Interface reconfig_mgmt_ Avalon MM Registers Signal Integrity Features DFE ADCE ATX Tuning MIF Streamer PLL Reconfig EyeQ PMA Analog DCD Calibration EyeQ DFE PMA ADCE ATX Streamer PLL DCD S M Embedded Controller 16 12 Transceiver Re...

Page 530: ...rocess variations to achieve optimal performance Offset cancellation runs only once upon power up The RX buffers are unavailable while this function is running This calibration feature is run automatically and enabled by default Arria V and Cyclone V devices do not require offset cancellation for the RX buffer Duty Cycle Calibration The TX clocks generated by the CMU and travel across the clock ne...

Page 531: ... enabled with a reconfiguration controller and or if you are using ATX PLLs in your design then the reference clock to the PHY IP must be stable before the reconfiguration controller is taken out of reset state Transceiver Reconfiguration Controller PMA Analog Control Registers You can use the Transceiver Reconfiguration Controller to reconfigure the following analog controls Differential output v...

Page 532: ...lid data values Refer to the Arria V Device Datasheet the Cyclone V Device Datasheet or the Stratix V Device Datasheet for more information about the electrical characteristics of each device The final values are currently pending full characterization of the silicon Note All undefined register bits are reserved Table 16 10 PMA Offsets and Values Offset Bits R W Register Name Description 0x0 5 0 R...

Page 533: ...use to update PMA settings Related Information Arria V Device Datasheet Cyclone V Device Datasheet Stratix V Device Datasheet Application Note 645 Dynamic Reconfiguration of PMA Controls in Stratix V Devices Transceiver Reconfiguration Controller EyeQ Registers EyeQ is a debug and diagnostic tool that analyzes the incoming data including the receiver s gain noise level and jitter after the receive...

Page 534: ...er which is typical in most data streams The following table lists the memory mapped EyeQ registers that you can access using Avalon MM reads and writes on reconfiguration management interface Note All channels connected to same Transceiver Reconfiguration Controller IP Core share one set of bit error rate block counters You can monitor one channel at a time If Transceiver Reconfigura tion Control...

Page 535: ...on Controller IP Core GUI When set to 1 the counters accumulate bits and errors When set to 0 pauses accumulation preserving the current values 1 RW BERB Enable Only available when you turn on the Enable Bit Error Rate Block in the Transceiver Reconfigura tion Controller IP Core GUI When set to 1 enables the BER When set to 0 disables the BER counters and the bit checker 0 RW Enable Eye Monitor Wr...

Page 536: ...31 0 R Bit Counter 31 0 Only valid when the BERB Enable and Counter Enable bits are set Bit Counter 63 0 reports the total number of bits received since you enabled or reset BER counters Each increment represents 256 bits 0x6 31 0 R Bit Counter 63 32 0x7 31 0 R Err Counter 31 0 Only available when the BERB Enable and Counter Enable bits are set Err Counter 63 0 reports the total number of error bi...

Page 537: ...tomatically runs offset calibration and phase interpolator PI phase calibration on all channels after power up You can run DFE manually to determine the optimal settings by monitoring the BER of the received data at each setting and specify the DFE settings that yield the widest eye Note If you are using the EyeQ monitor with DFE enabled you must put the EyeQ monitor in 1D mode by writing the EyeQ...

Page 538: ...s R W Register Name Description 0x0 1 RW power on Writing a 0 to this bit powers down DFE in the channel specified 0 RW adaptation engine enable Writing a 1 enables the adaptive equalization engine 0x1 3 0 RW tap 1 Specifies the coefficient for the first post tap The valid range is 0 15 0x2 3 RW tap 2 polarity Specifies the polarity of the second post tap as follows 0 negative polarity 1 positive ...

Page 539: ...lon MM reads and writes to configure the DFE and to turn it on and off There are three ways to control the DFE using a sequence of register based reconfiguration reads and writes Turning on DFE Continuous Adaptive mode Complete the following steps to turn on DFE continuous adaptive mode 1 Read the DFE control and status register busy bit bit 8 until it is clear 2 Write the logical channel number o...

Page 540: ...ster write bit to 1 b1 This turns on DFE power and initiates triggered DFE mode 6 Read the DFE control and status register busy bit bit 8 until it is clear 7 When busy equals 1b 0 the Transceiver Reconfiguration Controller has updated the logical channel specified in Step 2 with the data specified in Steps 3 and 4 The register based write to turn on the triggered DFE mode for logical channel 0 is ...

Page 541: ...nel 0 as shown in the following example Example 16 3 Register Based Write To Use DFE in Manual Mode and Set the First DFE Tap Value to 5 for Logical Channel 0 Setting logical channel 0 write_32 0x18 0x0 Setting DFE offset to 0x0 write_32 0x1B 0x0 Setting data register to 2 write_32 0x1C 0x2 Writing the data to use DFE in Manual mode write_32 0x1A 0x1 Setting DFE offset to 0x1 write_32 0x1B 0x1 Set...

Page 542: ...rted indicates that a reconfiguration operation is in progress 1 W Read Writing a 1 to this bit triggers a read operation 0 W Write Writing a 1 to this bit triggers a write operation 7 h2B 3 0 RW aeq_offset Specifies the address of the AEQ register to be read or written Refer to Table 16 16 for details 7 h2C 15 0 RW data Specifies the read or write data The following table describes the AEQ regist...

Page 543: ... can use this value as a reference Although automatic and manual equalization do not provide identical functionality specifying this value enables manual equalization to approximate the original setting 4 b0000 Refer to Changing Transceiver Settings Using Register Based Reconfiguration for the procedures you can use to control AEQ Transceiver Reconfiguration Controller ATX PLL Calibration Register...

Page 544: ...ect accesses on the reconfiguration bus Refer to Table 16 18 for offsets and values 7 h34 15 0 RW data Reconfiguration data for the transceiver PHY registers Table 16 18 ATX PLL Tuning Offsets and Values Offset Bits R W Register Name Description 0x0 0 RW Control Writing a 1 to this bit triggers ATX PLL calibration This register self clears Unused bits of this register must be set to 0 The tx_cal_b...

Page 545: ...sceiver PHY IP core The Reconfiguration tab allows you to specify up to five input reference clocks and up to four TX PLLs You can also change the input clock source to the CDR PLL up to five input clock sources are possible If you plan to dynamically reconfigure the PLLs in your design you must also enable Allow PLL Reconfiguration and specify the Main TX PLL logical index which is the PLL that t...

Page 546: ...ower Down in Arria V Devices For Cyclone V devices refer to Transceiver Reset Control and Power Down in Cyclone V Devices When you specify multiple PLLs you must use the QSF assignment XCVR_TX_PLL_RECONFIG_GROUP to identify the PLLs within a reconfiguration group using the Assignment Editor The XCVR_TX_PLL_RECONFIG_GROUP assignment identifies PLLs that the Quartus II Fitter can merge You can assig...

Page 547: ...he reference clock for the TX PLL you must specify the PLL s logical channel number When reconfi guring the reference clock for the CDR you must specify the channel s logical channel number 7 h42 9 R control and status When asserted indicates an error This bit is asserted if any of the following conditions occur The channel address is invalid The PHY address is invalid The address offset is invali...

Page 548: ...e MIF mode 0 and stream the ATX PLL MIF 0x1 2 0 RW logical PLL selection When written initiates a clock generation block CGB switch to logical PLL indexed by bits 2 0 This index refers to the Number of TX PLLs selected on the Reconfigu ration tab You can specify up to 4 input clocks If you set the Main TX PLL logical index to 0 the Quartus II software initializes your design using the first PLL de...

Page 549: ...e Description 0x0 5 0 RW dcd_control Writing 1 b1 to this bit to manually triggers DCD calibration Transceiver Reconfiguration Controller Channel and PLL Reconfiguration You can use channel and PLL reconfiguration to dynamically reconfigure the channel and PLL settings in a transceiver PHY IP core Among the settings that you can change dynamically are the data rate and interface width Refer to Dev...

Page 550: ...ansceiver PHY IP core The following table illustrates this point for the 10G datapath showing three examples where the FPGA fabric interface width is less than 64 bits Table 16 23 Channel Reconfiguration Bit Ordering Number of Lanes Specified FPGA Fabric Width Total Bits Default Channel Width Total Bits Used Bits 1 32 bits 32 bits 64 bits lane 64 bits Lane 0 31 0 2 40 bits 80 bits 64 bits lane 128...

Page 551: ...l address is invalid The PHY address is invalid The offset register address is invalid 8 R Busy When asserted indicates that a reconfi guration operation is in progress 3 2 RW Mode The following encodings are defined 2 b00 MIF This mode continuously reads and transfers a mif file which contains the reconfiguration data 2 b01 Direct Write In this mode you specify a logical channel a register offset...

Page 552: ...fied in the offset register When MIF Mode 2 b01 data holds an update for transceiver to be dynamically reconfigured Note All undefined register bits are reserved Table 16 25 Streamer Module Internal MIF Register Offsets Offset Bits R W Register Name Description 0x0 31 0 RW MIF base address Specifies the MIF base address 0x1 2 RW Clear error status Writing a 1 to this bit clears any error currently...

Page 553: ...amer Module Registers Mode 0 simplifies the reconfiguration process because all reconfi guration data is stored in the MIF which is streamed to the transceiver PHY IP in a single step The MIF can change PLL settings reference clock inputs or the TX PLL selection After the MIF streaming update is complete all transceiver PHY IP core settings reflect the value specified by the MIF Refer to Streamer ...

Page 554: ...tially specified data rate to a new data rate you can use the MIF streaming function to load the other mif Note When reconfiguration is limited to a few settings you can create a partial mif that only includes the settings that must be updated Refer to Reduced MIF Creation for more information about creating a partial mif file Example 16 4 Quartus II Generated MIF Files project_dir reconfig_mif in...

Page 555: ...ot zero indicates a data record For a non data record the opcode is represented by the lower 5 bits in the record Table 16 26 Opcodes for MIF Files Opcode Opcode Description 5 b00000 Reserved 5 b00001 Start of MIF 5 b00010 Channel format indicator specifying the MIF channel type The following encodings are defined 3 b000 Duplex channel 3 b001 TX PLL CMU 3 b010 RX only channel 3 b011 TX only channe...

Page 556: ...ength 0 Reserved Opcode End of MIF Length 3 Offset Address N Data for Offset N Length 1 Offset M Data for Offset M Data for Offset N 1 Data for Offset N 2 Length 2 Offset Address L Data for Offset L Data for Offset L 1 15 11 10 5 0 4 xcvr_diffmifgen Utility This section describes the xcvr_diffmifgen utility The xcvr_diffmifgen utility allows you to create a mif file that includes the differences i...

Page 557: ...MIF files as described in MIF Format The reduced MIF file preserves the lines shown in the following table Table 16 28 Required Lines for All MIFs Line Number Description Content Includes 0 Specifies start of the reconfiguration MIF Start of MIF opcode 1 Specifies the type of MIF Type of MIF opcode 2 Specifies the reference clock RefClk switch opcode 3 Specifies the PLL switch CGB PLL switch opcod...

Page 558: ...ated by the xcvr_diffmifgen utility Example 16 7 Reduced MIF File to_MIF_A Note The xcvr_diffmif utility only works for Quartus II post fit simulation and hardware UG 01080 2015 01 19 xcvr_diffmifgen Utility 16 41 Transceiver Reconfiguration Controller IP Core Overview Altera Corporation Send Feedback ...

Page 559: ...ransceiver settings You generate the reconfigured MIF by modifying the original transceiver settings For example if the original compilation specifies a clock divider value of 1 and the reconfigured compilation specifies a clock divider value of 2 the MIF files reflect that change The reduced MIF contains only the changed content In this example the difference between the two MIFs would be the clo...

Page 560: ...er Based Read of Logical Channel 2 Pre Emphasis Pretap Setting System Console is used for the following settings Setting logical channel 2 write_32 0x8 0x2 Setting offset to pre emphasis pretap write_32 0xB 0x1 Writing the logical channel and offset for pre emphasis pretap write_32 0xA 0x2 Reading data register for the pre emphasis pretap value read_32 0xC Changing Transceiver Settings Using Strea...

Page 561: ...1 0 0 0 1 1 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 Length 3 OffsetValue 0 Offset Data 15 1110 0 For the sample data record the length field specifies three data records The offset value is 0 as indicated by bits 10 0 The offset data are the three subsequent entries The following example performs a direct write in Streamer mode 1 This example writes the sample MIF into the Streamer module ...

Page 562: ...tents of a MIF file through the Streamer Module 1 Write the logical channel number to the Streamer logical channel register 2 Write MIF mode 2 b00 to the Streamer control and status register mode bits 3 Write the MIF base address 0x0 to the Streamer offset register 4 Write the base address of the MIF file to the Streamer data register 5 Write the Streamer control and status register write bit to 1...

Page 563: ...e control and status register busy bit 7 h3A bit 8 until it is clear 2 Write the Streamer Module logical channel number to the Streamer logical channel number register at address 0x38 3 Set the Streamer Module control and status register Mode bits 7 h3A bits 3 2 to 1 4 Determine the PRBS pattern from the table above and note the corresponding word aligner size and word aligner pattern The word ali...

Page 564: ...mer module to enable the PRBS generator in the Standard PCS 1 Read the Streamer Module control and status register busy bit 7 h3A bit 8 until it is clear 2 Write the Streamer Module logical channel number to the Streamer logical channel number register at address 0x38 3 Set the Streamer Module control and status register Mode bits 7 h3A bits 3 2 to 1 4 Determine the PRBS pattern from Word Aligner ...

Page 565: ... be modified 8 Write the new value from step 7 to the Streamer data register at address 0x3C 9 Write the Streamer control and status register 7 h3A with a value of 0x5 10 Repeat steps 3 9 to the TX PRBS Clock Enable 0x137 for RX PRBS Clock Enable 0x164 11 Assert the channel resets Note You can only enable one of the three pattern generators at a time Example 16 12 Enable the PRBS 31 Generator PRBS...

Page 566: ...e of 0x5 to address 0x3A Generator clock setup read_32 0x3A Read the control and status register busy bit 8 until it is clear write_32 0x38 0x0 write logical channel to 0x38 write_32 0x3A 0x4 set the MIF mode 1 to address 0x3A write_32 0x3B 0x137 write the pattern type offset write_32 0x3A 0x6 write the control and status register with a value of 0x6 to address 0x3A to initiate a read read_32 0x3C...

Page 567: ...to save them while performing the read modify write operations Understanding Logical Channel Numbering This discussion of channel numbering uses the following definitions Reconfiguration interface A bundle of signals that connect the Transceiver Reconfiguration Controller to a transceiver PHY data channel or TX PLL Logical channels An abstract representation of a channel or TX PLL that does not in...

Page 568: ...econfiguration interfaces 32 63 are for the TX PLLs Figure 16 9 Low Latency Transceiver PHY Example Note After Quartus II compilation many of the interfaces are merged The following figure illustrates the GUI for the Transceiver Reconfiguration Controller To connect the Low Latency PHY IP Core instance to the Transceiver Reconfiguration Controller you would enter 64 for Number of reconfiguration i...

Page 569: ... as a single bus of concatenated reconfiguration interfaces that grows linearly with the number of reconfiguration interfaces Although you must create a separate logical reconfiguration interface for each PHY IP core instance when the Quartus II software compiles your design it reduces original number of logical interfaces by merging them Allowing the Quartus II software to merge reconfiguration i...

Page 570: ...PLLs in each transceiver PHY instance to a single physical TX PLL Figure 16 11 Interface Ordering with Multiple Transceiver PHY Instances to and from Embedded Controller Transceiver Reconfiguration Controller S Interfaces 0 7 Interfaces 8 15 Reconfig to and from Transceiver Transceiver PHY Instance 1 Avalon MM Streaming Data Streaming Data Transceiver PHY Instance 0 Avalon MM Interfaces 0 3 Data L...

Page 571: ...ess 0 accesses data channel 0 and logical address 8 accesses the TX PLL for data channel 0 logical address 1 accesses data channel 1 and logical address 9 accesses the TX PLL for data channel 1 and so on In simulation to reconfigure the TX PLL for channel 0 specify logical address 8 in the Streamer module s logical channel number The Streamer module maps the logical channel to the physical channel...

Page 572: ...2 Channel 3 3 CMU 0 4 8 12 Channel 4 4 Channel 5 5 CMU 5 7 13 15 Channel 6 6 Channel 7 7 Two PHY IP Core Instances Each with Non Bonded Channels This section describes two instances with non bonded channels For each transceiver PHY IP core instance the Quartus II software assigns the data channels sequentially beginning at logical address 0 and assigns the TX PLLs the subsequent logical addresses ...

Page 573: ...er Reconfiguration Controller to all of the transceiver channels and PLLs in your design You can also use multiple Transceiver Reconfiguration Controllers to facilitate placement and routing of the FPGA However the three upper or lower contiguous channels in a transceiver bank must be connected to the same reconfiguration controller The following figure illustrates connections between the Transcei...

Page 574: ...ic to prevent concurrent access The configu ration shown results in a Quartus II compilation error Figure 16 13 Incorrect Connections 3Transceiver Channels Transceiver Bank 3Transceiver Channels Not Allowed Custom 10 GBASE R 10 GBASE R Custom Custom CMU PLL Transceiver Reconfiguration Controller S to Embedded Processor Transceiver Reconfiguration Controller S to Embedded Processor Reconfig to and ...

Page 575: ...design when the Quartus II software compiles your design it reduces the number of reconfiguration interfaces by merging reconfiguration interfaces The synthesized design typically includes a reconfigura tion interface for at least three channels because three channels share an Avalon MM slave interface which connects to the Transceiver Reconfiguration Controller IP Core Conversely you cannot conne...

Page 576: ...de by writing the phy_serial_loopback register 0x061 using the Avalon MM PHY management interface except for the Native PHY IP In Native PHY IP you can enable the serial loopback mode by driving rx_seriallpbken input port to 1 b1 Also PCI Express supports reverse parallel loopback mode as required by the PCI Express Base Specification The following figure shows the datapath for serial loopback The...

Page 577: ...ut Serializer Rx PMA Serial loopback De serializer To FPGA fabric for verification Transceiver Related Information PCI Express Base Specification 16 60 Loopback Modes UG 01080 2015 01 19 Altera Corporation Transceiver Reconfiguration Controller IP Core Overview Send Feedback ...

Page 578: ... Synchronization of the reset inputs Hysteresis for PLL locked status inputs Configurable reset timings Automatic or manual reset recovery mode 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other word...

Page 579: ...reset Transmitter PLL 19 As figure illustrates the Transceiver PHY Reset Controller connects to a Transceiver PHY The Transceiver PHY Reset Controller IP Core drives TX and RX resets to the Transceiver PHY and receives status from the Transceiver PHY Depending on the components in the design the calibration busy signal may be an output of the Transceiver PHY or the Transceiver Reconfiguration Cont...

Page 580: ...e families Device Family Support Cyclone V devices Final Arria V devices Final Arria V GZ Final Stratix V devices Final Other device families No support Performance and Resource Utilization for Transceiver PHY Reset Controller This section describes the performance and resource utilization for the transceiver PHY reset controller Table 17 2 Reset Controller Resource Utilization Stratix V Devices T...

Page 581: ...on Number of transceiver channels 1 1000 Specifies the number of channels that connect to the Transceiver PHY Reset Controller IP core The upper limit of the range is determined by your FPGA architecture Number of TX PLLs 1 1000 Specifies the number of TX PLLs that connect to the Transceiver PHY Reset Controller IP core Input clock frequency 1 500 MHz Input clock to the Transceiver PHY Reset Contr...

Page 582: ... mode Auto Manual Expose Port Specifies the Transceiver PHY Reset Controller behavior when the pll_locked signal is deasserted The following modes are available Auto The associated tx_digital_reset controller automatically resets whenever the pll_locked signal is deasserted Manual The associated tx_digital_reset controller is not reset when the pll_locked signal is deasserted allowing you to choos...

Page 583: ... rx_is_lockedtodata signal for automatic reset control otherwise the inputs are ANDed to provide internal status for the shared reset controller rx_analogreset duration 1 999999999 Specifies the time in ns to continue to assert the rx_analogreset after the reset input and all other gating conditions are removed The value is rounded up to the nearest clock cycle The default value is 40 ns rx_digita...

Page 584: ...ed status input from each PLL When asserted indicates that the TX PLL is locked When deasserted the PLL is not locked There is one signal per PLL pll_select p n 1 0 Input Synchronous to the Transceiver PHY Reset Controller input clock Set to zero when not using multiple PLLs When you select Use separate TX reset per channel this bus provides enough inputs to specify an index for each pll_locked si...

Page 585: ...ce still requires a one time rising edge on pll_locked before proceeding When deasserted the associated tx_digitalreset controller automatically begins its reset sequence whenever the selected pll_locked signal is deasserted rx_manual n 1 0 Input Asynchronous This optional signal places rx_digitalreset logic controller under automatic or manual control In manual mode the rx_digital reset controlle...

Page 586: ...ck Analog reset for TX channels The width of this signal depends on the number of TX channels This signal is asserted when any of the following conditions is true reset is asserted pll_powerdown is asserted pll_cal_busy is asserted tx_cal_busy is asserted This signal follows pll_powerdown and is deasserted after pll_locked goes high tx_ready n 1 0 Output Synchronous to the Transceiver PHY Reset Co...

Page 587: ... to the Transceiver PHY Reset Controller input clock Status signal to indicate when the RX reset sequence is complete This signal is deasserted while the RX reset is active It is asserted a few clock cycles after the deassertion of rx_ digitalreset Some protocol implementa tions may require you to monitor this signal prior to sending data The width of this signal depends on the number of RX channe...

Page 588: ... be lost if the IP is regenerated This skew is present whether you tie all tx_digitalresets together or you control them separately If your design includes the Transceiver PHY Reset Controller IP core you can substitute your instance and interface names for the generic names shown in the example Example 17 1 SDC Constraint for TX Digital Reset When Bonded Clocks Are Used set_max_skew from IP_INSTA...

Page 589: ...fer to the SDC and TimeQuest API Reference Manual Related Information SDC and TimeQuest API Reference Manual 17 12 Timing Constraints for Bonded PCS and PMA Channels UG 01080 2015 01 19 Altera Corporation Transceiver PHY Reset Controller IP Core Send Feedback ...

Page 590: ... to point connections between ext_pll_clk p 1 0 and the CMU ATX and fractional PLLs required 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service mar...

Page 591: ...t Use external TX PLL in the Native PHY GUI and instantiate all PLLs externally as shown in the figure above Dynamic reconfiguration is only supported for non bonded configurations Dynamic reconfiguration allows you to implement the following features TX PLL reconfiguration between up to 5 input reference clocks PLL switching using the x1 clock lines within a transceiver triplet PLL switching usin...

Page 592: ... if you plan to reconfigure the PLLs in your design This option is also required to simulate PLL reconfiguration Number of TX reference clocks 1 5 Specifies the number of reference clocks inputs to the Transceiver PLL PLL feedback path Internal External Select the External feedback path for the CPRI protocol to improve clock jitter by using an external voltage controlled crystal oscillator VCXO Se...

Page 593: ...nals PLLClock andStatus PLL Inputs Dynamic Reconfiguration optional Signal Name Direction Description pll_powerdown Input When asserted powers down the PLL pll_refclk Input Input reference clock for the CMU PLL pll_fbclk Input The feedback input port for the PLL pll_clkout Output Output clock from the PLL pll_locked Output When asserted indicates that the PLL has locked to the input reference cloc...

Page 594: ...elated Information Component Interface Tcl Reference UG 01080 2015 01 19 Transceiver PLL Signals 18 5 Transceiver PLL IP Core for Stratix V Arria V and Arria V GZ Devices Altera Corporation Send Feedback ...

Page 595: ... steps to specify a 3 0V supply for the VCCA voltage and a 1 0V supply to the VCCR voltages 1 On the Assignments menu select Assignment Editor The Assignment Editor appears 2 Complete the following steps for each pin requiring the VCCA voltage a Double click in the Assignment Name column and scroll to the bottom of the available assignments b Select VCCA_GXB Voltage c In the Value column select 3_...

Page 596: ...alog parameters the default value listed is for the initial setting not the recomputed setting The parameters are listed in alphabetical order For more information about the Pin Planner refer to About the Pin Planner in Quartus II Help For more information about the Assignment Editor refer to About the Assignment Editor in Quartus II Help For more information about Quartus II Settings refer to Qua...

Page 597: ...ESISTOR Use this assignment when the dedicated transceiver reference clock pins are fed by a DC coupled signal This option does not implement internal on chip termination or signal biasing You must implement termination and signal biasing outside of the FPGA This assignment is recommended for compliance with the PCI Express Card Electromechanical Specification Rev 2 0 and the HCSL IO Standard Opti...

Page 598: ...l or computed default values You may want to optimize some of these settings The default value is shown in bold type For computed analog parameters the default value listed is for the initial setting not the recomputed setting The parameters are listed in alphabetical order CDR_BANDWIDTH_PRESET Pin Planner and Assignment Editor Name CDR Bandwidth Preset Description Specifies the CDR bandwidth pres...

Page 599: ...nalog Settings Protocol Description Specifies the protocol that a transceiver implements When you use this setting for fully characterized devices the Quartus II software automatically sets the optimal values for analog settings including the VOD pre emphasis and slew rate For devices that are not fully characterized the Quartus II software specifies these settings using preliminary data If you as...

Page 600: ...tive sv_xcvr_native inst_sv_xcvr_native sv_pma inst_sv_pma sv_rx_pma rx_pma sv_rx_pma_inst rx_pmas 8 rx_pma rx_pma_buf Only one QSF setting for the parameter is allowed Options The following protocol values are defined BASIC CPRI PCIE_GEN1 PCIE_GEN2 SATA1_I SATA1_M SATA2_1 SATA2_M SATA2_X SRIO XAUI Assign To Pin TX and RX serial data XCVR_RX_COMMON_MODE_VOLTAGE Pin Planner and Assignment Editor Na...

Page 601: ...ables the receiver signal detection unit During normal operation NORMAL_SD_ON FALSE otherwise POWER_DOWN_SD TRUE Used for the PCIe PIPE PHY SATA and SAS protocols Options FALSE TRUE Assign To Pin RX serial data XCVR_RX_SD_OFF Pin Planner and Assignment Editor Name Receiver Cycle Count Before Signal Detect Block Declares Loss Of Signal Description Number of parallel cycles to wait before the signal...

Page 602: ...age Threshold Description Specifies signal detection voltage threshold level Vth The following encodings are defined SDLV_50MV 7 SDLV_45MV 6 SDLV_40MV 5 SDLV_35MV 4 SDLV_30MV 3 SDLV_25MV 2 SDLV_20MV 1 SDLV_15MV 0 Only used for the PCIe PIPE PHY SATA and SAS protocols The signal detect output is high when the receiver peak to peak differential voltage diff p p Vth x 4 For example a setting of 6 tra...

Page 603: ...ap Description Specifies the first post tap setting value Note Legal values for this parameter vary with the data pattern and data rate Refer to the Arria V Device Datasheet for more information Options 0 31 Assign To Pin TX serial data Related Information Arria V Device Datasheet XCVR_TX_RX_DET_ENABLE Pin Planner and Assignment Editor Name Transmitter Receiver Detect Block Enable Description Enab...

Page 604: ...Assignment Editor Name Transmitter Differential Output Voltage Description Differential output voltage setting The values are monotonically increasing with the driver main tap current strength Options 0 63 Assign To Pin TX serial data XCVR_TX_VOD_PRE_EMP_CTRL_SRC Pin Planner and Assignment Editor Name Transmitter VOD Pre emphasis Control Source 19 10 XCVR_TX_RX_DET_MODE UG 01080 2015 01 19 Altera ...

Page 605: ...ault value is shown in bold type For computed analog parameters the default value listed is for the initial setting not the recomputed setting The parameters are listed in alphabetical order For more information about the Pin Planner refer to About the Pin Planner in Quartus II Help For more information about the Assignment Editor refer to About the Assignment Editor in Quartus II Help For more in...

Page 606: ..._EXTERNAL_RESISTOR Use this assignment when the dedicated transceiver reference clock pins are fed by a DC coupled signal This option does not implement internal on chip termination or signal biasing You must implement termination and signal biasing outside of the FPGA This assignment is recommended for compliance with the PCI Express Card Electromechanical Specification Rev 2 0 and the HCSL IO St...

Page 607: ...pma rx_pma_buf Only one QSF setting for the parameter is allowed Options All_Stages_Enabled Bypass_Stages Assign To Pin RX serial data Note This setting can be used for data rates upto 5 Gbps for backplane applications and 8 Gbps for chip to chip applications XCVR_TX_SLEW_RATE_CTRL Pin Planner and Assignment Editor Name Transmitter Slew Rate Control Description Specifies the slew rate of the outpu...

Page 608: ...n selecting a value Options 0_85V 1_0V Assign To Pin TX RX serial data Related Information Arria V GX GT GZ SX and ST Device Datasheet Analog Settings Having Global or Computed Default Values for Arria V GZ Devices The following analog parameters have global or computed default values You may want to optimize some of these settings The default value is shown in bold type For computed analog parame...

Page 609: ... PLL that is in the same transceiver bank Available for Gen1 Gen2 and Gen3 variants Example set_parameter name master_ch_number 4 to design pcie_i altera_xcvr_pipe design _inst sv_xcvr_pipe_nr pipe_nr_inst sv_xcvr_pipe_native transceiver_core Options 1 4 Assign To Include in qsf file Related Information Transceiver Configurations in Arria V GZ Devices Refer to Advance SIC Channel Placement Guideli...

Page 610: ...onfigurations in Arria V GZ Devices Refer to Advance SIC Channel Placement Guidelines for PIPE Configurations in this document XCVR_ANALOG_SETTINGS_PROTOCOL Pin Planner and Assignment Editor Name Transceiver Analog Settings Protocol Description Specifies the protocol that a transceiver implements When you use this setting for fully characterized devices the Quartus II software automatically sets t...

Page 611: ...cvr_pipe_native g_xcvr sv_xcvr_pipe_native sv_xcvr_native inst_sv_xcvr_native sv_pma inst_sv_pma sv_rx_pma rx_pma sv_rx_pma_inst rx_pmas 8 rx_pma rx_pma_buf Only one QSF setting for the parameter is allowed Options The following protocol values are defined BASIC CEI CPRI INTERLAKEN PCIE_GEN1 PCIE_GEN2 PCIE_GEN3 QPI SFIS SONET SRIO TENG_1588 TENG_BASER TENG_SDI XAUI Assign To Pin TX and RX serial d...

Page 612: ...ommon Mode Voltage Description Receiver buffer common mode voltage Note Contact Altera for using this assignment Related Information How to Contact Altera on page 21 42 XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE Pin Planner and Assignment Editor Name Receiver Linear Equalizer Control PCI Express Description If enabled equalizer gain control is driven by the PCS block for PCI Express If disabled equa...

Page 613: ... Signal Detect Block Declares Loss Of Signal Description Number of parallel cycles to wait before the signal detect block declares loss of signal Only used for the PCIe PIPE PHY SATA and SAS protocols Options 0 29 Assign To Pin RX serial data XCVR_RX_SD_ON Pin Planner and Assignment Editor Name Receiver Cycle Count Before Signal Detect Block Declares Presence Of Signal Description Number of parall...

Page 614: ... peak to peak differential voltage diff p p Vth x 4 For example a setting of 6 translates to peak to peak differential voltage of 180mV 4 45mV The Vdiff p p must be 180mV to turn on the signal detect circuit Options 0 7 Assign To Pin RX serial data XCVR_TX_COMMON_MODE_VOLTAGE Pin Planner and Assignment Editor Name Transmitter Common Mode Driver Voltage Description Transmitter common mode driver vo...

Page 615: ...691 This solution provides the mapping of the Transceiver Toolkit pretap settings to the Quartus II transceiver QSF assignment Stratix V Device Datasheet XCVR_TX_PRE_EMP_2ND_POST_TAP_USER Pin Planner and Assignment Editor Name Transmitter Preemphasis Second Post Tap user Description Specifies the transmitter pre emphasis second post tap setting value including inversion Options 0 31 Assign To Pin ...

Page 616: ...post tap setting value Note This parameter must be set in conjunction with XCVR_TX_VOD XCVR_TX_PRE_EMP_1ST_POST_TAP and XCVR_TX_PRE_EMP_PRE_TAP All combinations of these settings are not legal Refer to the Arria V GZ Device Datasheet for more information Options 0 15 Assign To Pin TX serial data Related Information Arria V GZ Device Datasheet XCVR_TX_PRE_EMP_INV_2ND_TAP Pin Planner and Assignment ...

Page 617: ...tion rd02262013_691 This solution provides the mapping of the Transceiver Toolkit pretap settings to the Quartus II transceiver QSF assignment XCVR_TX_PRE_EMP_PRE_TAP Pin Planner and Assignment Editor Name Transmitter Pre emphasis Pre Tap Description Specifies the pre tap pre emphasis setting Note This parameter must be set in conjunction with XCVR_TX_VOD XCVR_TX_PRE_EMP_1ST_POST_TAP and XCVR_TX_P...

Page 618: ...ignment Editor Name Transmitter Receiver Detect Block Mode Description Sets the mode for receiver detect block Options 0 15 Assign To Pin TX serial data XCVR_TX_RX_DET_OUTPUT_SEL Pin Planner and Assignment Editor Name Transmitter s Receiver Detect Block QPI PCI Express Control Description Determines QPI or PCI Express mode for the Receiver Detect block Options RX_DET_QPI_ OUT RX_DET_PCIE_ OUT 19 2...

Page 619: ...more information Options 0 63 50 Assign To Pin TX serial data Related Information Arria V GZ Device Datasheet XCVR_TX_VOD_PRE_EMP_CTRL_SRC Pin Planner and Assignment Editor Name Transmitter VOD Pre emphasis Control Source Description When set to DYNAMIC_CTL the PCS block controls the VOD and pre emphasis coefficients for PCI Express When this assignment is set to RAM_CTL the VOD and pre emphasis a...

Page 620: ...on chip termination and on chip signal biasing DC_COUPLING_ INTERNAL_100_OHMS Used this setting when the dedicated transceiver reference clock pins are fed by a DC coupled signal whose Vcm meets the device specification This assignment implements internal on chip termination but not on chip signal biasing DC_COUPLING_EXTERNAL_RESISTOR Use this assignment when the dedicated transceiver reference cl...

Page 621: ...B voltage for an GXB I O pin by specifying the intended supply voltages for a GXB I O pin Options 1_1V 1_2V Assign To Pin TX RX serial data Analog Settings Having Global or Computed Values for Cyclone V Devices The following analog parameters have global or computed default values You may want to optimize some of these settings The default value is shown in bold type For computed analog parameters...

Page 622: ...nner and Assignment Editor Name Transceiver Analog Settings Protocol Description Specifies the protocol that a transceiver implements When you use this setting for fully characterized devices the Quartus II software automatically sets the optimal values for analog settings including the VOD pre emphasis and slew rate For devices that are not fully characterized the Quartus II software specifies th...

Page 623: ...pipen1b sv_xcvr_pipe_native g_xcvr sv_xcvr_pipe_native sv_xcvr_native inst_sv_xcvr_native sv_pma inst_sv_pma sv_rx_pma rx_pma sv_rx_pma_inst rx_pmas 8 rx_pma rx_pma_buf Only one QSF setting for the parameter is allowed Options The following protocol values are defined BASIC CPRI PCIE_GEN1 PCIE_GEN2 SRIO XAUI Assign To Pin TX and RX serial data XCVR_RX_DC_GAIN Pin Planner and Assignment Editor Name...

Page 624: ...o Contact Altera on page 21 42 XCVR_RX_SD_ENABLE Pin Planner and Assignment Editor Name Receiver Signal Detection Unit Enable Disable Description Enables or disables the receiver signal detection unit During normal operation NORMAL_SD_ON FALSE otherwise POWER_DOWN_SD TRUE Used for the PCIe PIPE PHY SATA and SAS protocols Options FALSE TRUE Assign To Pin RX serial data XCVR_RX_SD_OFF Pin Planner an...

Page 625: ...t block declares presence of signal Only used for the PCIe PIPE PHY SATA and SAS protocols Options 0 16 1 Assign To Pin RX serial data XCVR_RX_SD_THRESHOLD Pin Planner and Assignment Editor Name Receiver Signal Detection Voltage Threshold Description Specifies signal detection voltage threshold level Vth The following encodings are defined SDLV_50MV 7 SDLV_45MV 6 SDLV_40MV 5 SDLV_35MV 4 SDLV_30MV ...

Page 626: ...de driver voltage Note Contact Altera for using this assignment Related Information How to Contact Altera on page 21 42 XCVR_TX_PRE_EMP_1ST_POST_TAP Pin Planner and Assignment Editor Name Transmitter Pre emphasis First Post Tap Description Specifies the first post tap setting value Note Legal values for this parameter vary with the data pattern and data rate Refer to the Cyclone V Device Datasheet...

Page 627: ...ceiver Detect Block Mode Description Sets the mode for receiver detect block Options 0 15 Assign To Pin TX serial data XCVR_TX_VOD Pin Planner and Assignment Editor Name Transmitter Differential Output Voltage Description Differential output voltage setting The values are monotonically increasing with the driver main tap current strength Options 0 63 Assign To Pin TX serial data UG 01080 2015 01 1...

Page 628: ...se original values are place holders for the values that match your electrical board specification The default value of an analog parameter is shown in bold type The parameters are listed in alphabetical order Related Information PCI Express Card Electromechanical Specification Rev 2 0 Stratix V Device Datasheet About the Pin Planner About the Assignment Editor Quartus II Settings File Manual XCVR...

Page 629: ...s Use it for AC coupled signals This setting implements on chip termination and on chip signal biasing DC_COUPLING_ INTERNAL_100_OHMS Used this setting when the dedicated transceiver reference clock pins are fed by a DC coupled signal whose Vcm meets the device specification This assignment implements internal on chip termination but not on chip signal biasing DC_COUPLING_EXTERNAL_RESISTOR Use thi...

Page 630: ... value on instance pci_interface_ddf2 u_pci_interface_2 PCIE_8x8Gb_HARDIP_2 PCIe2_Interface U_PCIE_CORE altpcie_sv_hip_ast_hwtcl pcie_8x8gb_hardip_2_inst altpcie_hip_256_pipen1b altpcie_hip_256_pipen1b sv_xcvr_pipe_native g_xcvr sv_xcvr_pipe_native sv_xcvr_native inst_sv_xcvr_native sv_pma inst_sv_pma sv_rx_pma rx_pma sv_rx_pma_inst rx_pmas 8 rx_pma rx_pma_buf Only one QSF setting for the paramete...

Page 631: ... GXB I O pin If you do not make this assignment the compiler automatically sets the correct VCCA_GXB voltage depending on the configured data rate as follows Data rate 6 5 Gbps 2_5V Data rate 6 5 Gbps 3_0V Options 2_5V 3_0V Assign To Pin TX RX serial data XCVR_VCCR_VCCT_VOLTAGE Pin Planner and Assignment Editor Name VCCR_GXB VCCT_GXB Voltage Description Refer to the Device Datasheet for Stratix V ...

Page 632: ...anner and Assignment Editor Name Parameter Assignment Editor Only Description For the PHY IP Core for PCI Express PIPE specifies the channel number of the channel acting as the master channel for a single transceiver bank or 2 adjacent banks This setting allows you to override the default master channel assignment for the PCS and PMA The master channel must use a TX PLL that is in the same transce...

Page 633: ...tions in Stratix V Devices Refer to Advance SIC Channel Placement Guidelines for PIPE Configurations in this document PLL_BANDWIDTH_PRESET Pin Planner and Assignment Editor Name PLL Bandwidth Preset Description Specifies the PLL bandwidth preset setting Options Auto Low Medium High Assign To PLL instance reserved_channel Pin Planner and Assignment Editor Name Parameter Assignment Editor Only UG 01...

Page 634: ...ng the VOD pre emphasis and slew rate For devices that are not fully characterized the Quartus II software specifies these settings using preliminary data If you assign a value to XCVR_ANALOG_SETTINGS_PROTOCOL you cannot assign a value for any settings that this parameter controls For example for PCIe the XCVR_ANALOG_SETTINGS_PROTOCOL assigns a value to XCVR_RX_BYPASS_EQ_STAGES_234 If you also ass...

Page 635: ...eiver Buffer DC Gain Control Description Controls the RX buffer DC gain for GTchannels Options 0 19 8 Assign To Pin RX serial data XCVR_RX_DC_GAIN Pin Planner and Assignment Editor Name Receiver Buffer DC Gain Control Description Controls the RX buffer DC gain for GX channels Options 0 4 UG 01080 2015 01 19 XCVR_GT_RX_DC_GAIN 19 41 Analog Parameters Set Using QSF Assignments Altera Corporation Sen...

Page 636: ...on Receiver buffer common mode voltage This parameter is only for GT transceivers Note Contact Altera for using this assignment Related Information How to Contact Altera on page 21 42 XCVR_GT_RX_CTLE Pin Planner and Assignment Editor Name GT Receiver Linear Equalizer Control Description Static control for the continuous time equalizer in the receiver buffer The equalizer has 9 distinct settings fr...

Page 637: ...ith XCVR_GT_TX_PRE_EMP_PRE_TAP All combinations of these settings are not legal Refer to the Stratix V Device Datasheet for more information Options 0 31 5 Assign To Pin TX serial data Related Information Stratix V Device Datasheet XCVR_GT_TX_PRE_EMP_ INV_PRE_TAP Pin Planner and Assignment Editor Name GT Transmitter Pre emphasis Pre Tap Invert Description Inverts the transmitter pre emphasis pre t...

Page 638: ...erial data XCVR_GT_TX_VOD_MAIN_TAP Pin Planner and Assignment Editor Name GT Transmitter Differential Output Voltage Description Differential output voltage setting The values are monotonically increasing with the driver main tap current strength Options 0 5 3 Assign To Pin TX serial data XCVR_RX_COMMON_MODE_VOLTAGE Pin Planner and Assignment Editor Name Receiver Buffer Common Mode Voltage 19 44 X...

Page 639: ...control is determined by the XCVR_RX_LINEAR_EQUALIZER_SETTING Options TRUE FALSE Assign To Pin RX serial data XCVR_RX_SD_ENABLE Pin Planner and Assignment Editor Name Receiver Signal Detection Unit Enable Disable Description Enables or disables the receiver signal detection unit During normal operation NORMAL_SD_ON FALSE otherwise POWER_DOWN_SD TRUE Used for the PCIe PIPE PHY SATA and SAS protocol...

Page 640: ...Block Declares Presence Of Signal Description Number of parallel cycles to wait before the signal detect block declares presence of signal Only used for the PCIe PIPE PHY SATA and SAS protocols Options 0 16 Assign To Pin RX serial data XCVR_RX_SD_THRESHOLD Pin Planner and Assignment Editor Name Receiver Signal Detection Voltage Threshold Description Specifies signal detection voltage threshold lev...

Page 641: ...driver voltage Note Contact Altera for using this assignment Related Information How to Contact Altera on page 21 42 XCVR_TX_PRE_EMP_PRE_TAP_USER Pin Planner and Assignment Editor Name Transmitter Pre emphasis Pre Tap user Description Specifies the TX pre emphasis pretap setting value including inversion Note This parameter must be set in conjunction with XCVR_TX_VOD XCVR_TX_PRE_EMP_1ST_POST_TAP a...

Page 642: ...nner and Assignment Editor Name Transmitter pre emphasis First Post Tap Description Specifies the first post tap setting value Note This parameter must be set in conjunction with XCVR_TX_VOD XCVR_TX_PRE_EMP_2ND_POST_TAP and XCVR_TX_PRE_EMP_PRE_TAP All combinations of these settings are not legal Refer to the Stratix V Device Datasheet for more information Options 0 31 Assign To Pin TX serial data ...

Page 643: ...nsceiver QSF assignment Stratix V Device Datasheet XCVR_TX_PRE_EMP_INV_2ND_TAP Pin Planner and Assignment Editor Name Transmitter Preemphasis Second Tap Invert Description Inverts the transmitter pre emphasis 2nd post tap Options TRUE FALSE Assign To Pin TX serial data Related Information Solution rd02262013_691 This solution provides the mapping of the Transceiver Toolkit pretap settings to the Q...

Page 644: ... pre tap pre emphasis setting Note This parameter must be set in conjunction with XCVR_TX_VOD XCVR_TX_PRE_EMP_1ST_POST_TAP and XCVR_TX_PRE_EMP_2ND_POST_TAP All combinations of these settings are not legal Refer to the Stratix V Device Datasheet for more information Options 0 15 Assign To Pin TX serial data Related Information Stratix V Device Datasheet XCVR_TX_RX_DET_ENABLE Pin Planner and Assignm...

Page 645: ...SEL Pin Planner and Assignment Editor Name Transmitter s Receiver Detect Block QPI PCI Express Control Description Determines QPI or PCI Express mode for the Receiver Detect block Options RX_DET_QPI_ OUT RX_DET_PCIE_ OUT Assign To Pin TX serial data XCVR_TX_VOD Pin Planner and Assignment Editor Name Transmitter Differential Output Voltage UG 01080 2015 01 19 XCVR_TX_RX_DET_MODE 19 51 Analog Parame...

Page 646: ...d Information Stratix V Device Datasheet XCVR_TX_VOD_PRE_EMP_CTRL_SRC Pin Planner and Assignment Editor Name Transmitter VOD Pre emphasis Control Source Description When set to DYNAMIC_CTL the PCS block controls the VOD and pre emphasis coefficients for PCI Express When this assignment is set to RAM_CTL the VOD and pre emphasis are controlled by other assignments such as XCVR_TX_PRE_EMP_1ST_POST_T...

Page 647: ...ng the separately instantiated Transceiver Reconfiguration Controller Control of loopback modes is also different in Stratix IV and Stratix V devices For Stratix IV devices you must select loopback options in the using the MegaWizard Plug In Manager For Stratix V devices you control loopback modes through Avalon MM registers Table 20 1 Controlling Loopback Modes in Stratix IV and Stratix V Devices...

Page 648: ...0 The reconfiguration bus includes Avalon MM signals to read and write registers and memory and test bus signals When you instantiate a transceiver PHY in a Stratix V device the transceiver PHY IP core provides informational messages specifying the number of required reconfiguration interfaces in the message pane Example 20 1 Informational Messages for the Transceiver Reconfiguration Interface PHY...

Page 649: ... the Stratix IV Device Handbook Related Information ALTGX_RECONFIG Megafunction User Guide for Stratix IV Devices Differences Between XAUI PHY Parameters for Stratix IV and Stratix V Devices Table 20 2 Comparison of ALTGX Megafunction and XAUI PHY Parameters ALTGX Parameter Name Default Value XAUI PHY Parameter Name Comments Number of channels Number of XAUI interfaces In Stratix V devices this pa...

Page 650: ...ce 100 ohms VOD setting 4 Preemphasis 1st post tap 0 Preemphasis pre tap setting 0 Preemphasis second post tap setting 0 Analog controls Off Enable ADCE Off Not available as parameters in the MegaWizard Plug In Manager interface Not available in 10 0 Enable channel and transmitter PLL reconfig Off Starting channel number 0 No longer required Automatically set to 0 The Quartus II software handles l...

Page 651: ...rx_serial 3 0 tx_datain 16 n 1 0 xgmii_tx_dc 63 0 rx_dataout 16 n 1 0 xgmii_rx_dc 63 0 tx_dataout n 1 0 xaui_tx_serial 3 0 Optional TX and RX Status Ports gxb_powerdown n 4 1 0 Not available however you can access them through the Avalon MM PHY management interface pll_locked n 1 0 Not available rx_locktorefclk n 1 0 Not available rx_locktodata n 1 0 Not available rx_pll_locked n 4 1 0 Not availab...

Page 652: ... 0 Not available rx_rmfifodatadeleted 2 n 1 0 Not available Transceiver Reconfiguration cal_blk_clk 1 These signals are included in the reconfig_to_xcvr bus reconfig_clk 1 reconfig_togxb 3 0 reconfig_to_xcvr Variable reconfig_fromgxb 16 0 reconfig_from_xcvr Variable Avalon MM Management Interface Not Available phy_mgmt_clk_rst 1 phy_mgmt_clk 1 phy_mgmt_address 8 0 phy_mgmt_read 1 phy_mgmt_readdata...

Page 653: ...Subprotocol Protocol Version Input clock frequency PLL reference clock frequency Starting Channel Number Automatically set to 0 Quartus II software handles lane assignments Enable low latency sync pipe_low_latency_ syncronous_mode Enable RLV with run length of pipe_run_length_ violation_checking Always on Enable electrical idle inference functionality Enable electrical idle inferencing phy_mgmt_cl...

Page 654: ...ation Off TX Rterm 100 VCO control setting 5 Pre emphasis 1st post tap 18 Not available in MegaWizard Interface Use assignment editor to make these assignments Pre tap 0 2nd post tap 0 DPRIO VOD Pre em Eq and EyeQ Off DPRIO Channel and TX PLL Reconfig Off Differences Between PHY IP Core for PCIe PHY PIPE Ports for Stratix IV and Stratix V Devices This section lists the differences between the top ...

Page 655: ...a n d 1 0 tx_ctrlenable pipe_txdatak d 8 n 1 0 tx_detectrxloop pipe_txdetectrx_loopback n 1 0 tx_forcedispcompliance pipe_txcompliance n 1 0 tx_forceelecidle pipe_txelecidle n 1 0 txswing pipe_txswing n 1 0 tx_pipedeemph 0 pipe_txdeemph n 1 0 tx_pipemargin 2 0 pipe_txmargin 3 n 1 0 rateswitch 0 pipe_rate 1 0 n 1 0 powerdn pipe_powerdown 2 n 1 0 rx_elecidleinfersel pipe_eidleinfersel 3 n 1 0 rx_dat...

Page 656: ...rx_disperr d 8 n 1 0 rx_patterndetect d 8 n 1 0 tx_phase_comp_fifo_error n 1 0 rx_phase_comp_fifo_error n 1 0 rx_signaldetect n 1 0 rx_rlv n 1 0 rx_datain rx_serial_data n 1 0 tx_dataout tx_serial_data n 1 0 Reconfiguration cal_blk_clk These signals are included in the reconfig_to_xcvr bus 1 reconfig_clk 1 fixedclk 1 reconfig_togxb reconfig_to_xcvr Variable reconfig_fromgxb reconfig_from_xcvr Vari...

Page 657: ...Default Value Custom PHY Parameter Name General Not available Device family Transceiver protocol Mode of operation Enable bonding What is the number of channels Number of lanes Which subprotocol will you be using 4 8 Not available What is the channel width Serialization factor What is the effective data rate Data rate What is the input clock frequency Input clock frequency tx rx_8b_10b_mode Enable...

Page 658: ...f Run length What is the word alignment pattern Word alignment pattern What is the word alignment pattern length Word aligner pattern length Protocol Settings Rate match Byte order Rate Match What is the 20 bit rate match pattern1 usually used for ve disparity pattern Rate match insertion deletion ve disparity pattern What is the 20 bit rate match pattern1 usually used for ve disparity pattern Rat...

Page 659: ...the reconfig_to_xcvr bus reconfig_clk pll_inclk pll_ref_clk p 1 0 rx_coreclk rx_coreclkin tx_coreclk tx_coreclkin Avalon ST TX Interface tx_datain tx_parallel_data d n 1 0 tx_ctrlenable tx_datak d n 1 0 rx_ctrldetect rx_datak d n 1 0 Avalon ST RX Interface rx_dataout rx_parallel_data d n 1 0 rx_runningdisp rx_runningdisp d 8 n 1 0 rx_enabyteord rx_enabyteord n 1 0 High Speed Serial I O rx_datain r...

Page 660: ...iptions rx_phase_comp_fifo_error rx_seriallpbken tx_phase_comp_fifo_error tx_invpolarity Transceiver Reconfiguration reconfig_togxb 3 0 reconfig_to_xcvr Variable reconfig_fromgxb 16 0 reconfig_from_xcvr Variable Related Information Register Interface and Register Descriptions on page 9 27 23 n the number of lanes d the total deserialization factor from the pin to the FPGA fabric 20 14 Differences ...

Page 661: ... 4 3 10GBASE KR PHY Performance and Resource Utilization Changed the description of tx_invpolarity register and register address 0x22 in PMA Registers section Changed the descriptions of main_rc post_rc and pre_rc signals with example mappings in Dynamic Reconfiguration Interface Signals section 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and...

Page 662: ...iption of xgmii_tx_clk and xgmii_rx_clk in Table 6 10 Optional Clock and Reset Signals Interlaken PHY IP Core 2 7 Made the following changes Updated the chapter to indicate new IP instantiation flow using the IP Catalog Changed the device family support to final for this IP core in the Table 7 1 Device Family Support Updated the descriptions of rx_dataout_bp n and tx_user_ clkout signals in Table ...

Page 663: ...IP instantiation flow using the IP Catalog Changed the device family support fo final for this IP core in Table 10 1 Device Family Support Deterministic Latency PHY IP Core 2 7 Made the following changes Updated the chapter to indicate new IP instantiation flow using the IP Catalog Changed the device family support fo final for this IP core in Table 11 4 Device Family Support Updated Table PMA Dat...

Page 664: ... Updated the 10G PCS Interface section to indicate that 10G PCS interface signals are used when phase compensation FIFO is in FIFO mode Added a note to Table Status Flag Mappings for Simplified Native PHY Interface regarding EDB and PAD characters Arria V Transceiver Native PHY IP Core 2 7 Made the following changes Updated the chapter to indicate new IP instantiation flow using the IP Catalog Cha...

Page 665: ...le Status Flag Mappings for Simplified Native PHY Interface under Rate Match FIFO Parameters section Transceiver Reconfi guration Controller IP Core 2 7 Made the following changes Updated the chapter to indicate new IP instantiation flow using the IP Catalog Added an exception for Native PHY IP in the Loopback Modes section Changed the introductory sentence of MIF Reconfiguration Manage Avalon MM ...

Page 666: ...ded to use fractional PLL in fractional mode as a TX PLL or for PLL cascading Analog Parameters Set Using QSF Assignments 2 7 Made the following changes Removed references to SATA protocol from XCVR_ANALOG_ PROTOCOL QSF assignment Added a note related to data rate restriction for XCVR_RX_ BYPASS_EQ_STAGES_234 assignment Revision History for Previous Releases of the Transceiver PHY IP Core This sec...

Page 667: ...gmii_rx_clk signals in Table 4 11 XGMII and GMII Signals Updated the description of en_lcl_rxeq and rxeq_done signals in Table 4 17 Dynamic Reconfiguration Interface Signals Added a note about performing read modify writes for all registers in 10GBASE KR PHY Register Definitions section Added a clarification about reset sequencer in the 10GBASE KR PHY Clock and Reset Interfaces section on page 4 1...

Page 668: ...dded a clarification about reset sequencer in the 1G 10GbE PHY Clock and Reset Interfaces section on page 5 7 Updated tx_clkout_1g rx_clkout_1g tx_coreclkin_1g and rx_coreclkin_1g connections in Figure 5 3 Clocks for Standard and 10G PCS and TX PLLs XAUI 2 6 Added the statement This register is only available in the hard XAUI implementation for 0x82 and 0x83 polarity inversion for 0x082 and 0x083 ...

Page 669: ..._pma_qpipulldn signals in Table 12 38 Native PHY Common Interfaces Updated the descriptions of tx_cal_busy and rx_cal_busy interface signals Addedext_pll_clk signal to Figure 12 5 Stratix V Native PHY Common Interfaces and added its description in Table 12 38 Native PHY Common Interfaces Arria V Transceiver Native PHY IP Core 2 6 Made the following changes Removed the description for rx_clklow and...

Page 670: ...ef ports from Table 15 15 Native PHY Common Interfaces Removed the ports rx_clklow and rx_fref from Figure 15 3 Common Interfaces Ports Updated the descriptions of tx_cal_busy and rx_cal_busy interface signals Added ext_pll_clk signal to Figure 15 3 Common Interface Ports and added its description in Table 15 15 Native PHY Common Interfaces Transceiver Reconfi guration Controller IP Core Overview ...

Page 671: ...e FPGA fabric to PCS interface width is 64 bits Added the description for a new parameter PCS PMA interface width in General Option Parameters section Added frequency for rx_recovered_clk n 0 It s 257 8 MHz Updated the descriptions of rx_latency_adj_10g and tx_ latency_adj_10g Changed the width of these signals for all references Added description for Enable embedded reset controller parameter Gen...

Page 672: ...ection Custom PHY IP Core 2 5 Made the following changes Added information on bit mapping for tx_parallel_data and rx_parallel_data Changed the introduction of Optional Status Interfaces section This section applies for both TX and RX Added a note related to auto negotiation state machine in Rate Match FIFO Parameters section Updated the description of rx_bitslip signal Added SDC Timing Constraint...

Page 673: ... FIFO Parameters section Updated the description of rx_std_bitslip signal Updated the table for Signal Definitions for rx_parallel_data with and without 8B 10B Encoding Arria V GZ Transceiver Native PHY IP Core 2 5 Made the following changes Updated the description of Number of TX PLLs parameter in TX PMA Parameters table Updated the description of Selected Clock Network parameter in TX PLL Parame...

Page 674: ...Updated the description of rx_manual signal in Interfaces for Transceiver PHY Reset Controller section Updated the description of pll_select signal Added a new section Usage Examples for pll_select Analog Parameters Set Using QSF Assignments 2 5 Made the following changes Updated definitions of XCVR_RX_SD_ENABLE XCVR_RX_SD_OFF XCVR_RX_SD_ON and XCVR_RX_SD_THRESHOLD These settings are now available...

Page 675: ...LL merging using the XCVR_TX_PLL_ RECONFIG_GROUP QSF setting not the FORCE_MERGE_PLL QSF setting Arria V Native PHY 2 2 Correction You can specify PLL merging using the XCVR_TX_PLL_ RECONFIG_GROUP QSF setting not the FORCE_MERGE_PLL QSF setting Arria V GZ Native PHY 2 2 Correction You can specify PLL merging using the XCVR_TX_PLL_ RECONFIG_GROUP QSF setting not the FORCE_MERGE_PLL QSF setting Cycl...

Page 676: ...Core for PCI Express April 2013 2 1 No changes from previous release Custom PHY April 2013 2 1 No changes from previous release Low Latency PHY April 2013 2 1 No changes from previous release Deterministic Latency PHY April 2013 2 1 No changes from previous release Stratix V Native PHY April 2013 2 1 Removed Arria V GT sentence on first page Arria V Native PHY April 2013 2 1 No changes from previo...

Page 677: ... 2 1 No changes from previous release Analog Parameters Set Using QSF Assignment April 2013 2 1 Fix typo in the Analog Settings for Arria V GZ Devices table Migrating from Stratix IV to Stratix V Devices April 2013 2 1 No changes from previous release Date Document Version Changes Made Introduction March 2013 2 0 No changes from previous release Getting Started March 2013 2 0 No changes from previ...

Page 678: ...ed for this variant Added fact that RESTART_AUTO_NEGOTIATION bit is self clearing 0x90 bit 9 Added fact that half duplex mode is not supported 0x94 bit 6 Added fact that the next page bit is not supported 0x94 bit 15 XAUI March 2013 2 0 Added Arria V Arria V GZ and Cyclone V to the list of devices that do not support the pma_tx_pll_is_locked register in Table 6 15 XAUI PHY IP Core Registers Interl...

Page 679: ...0x3a Added SDC timing constraints Changed RX Equalization Control0x11 in Table 16 10 PMA Offsets and Values to RW This change is available starting with Quartus II 12 1 SP1 Clarified encodings for RX equalization DC gain in Table 16 10 PMA Offsets and Values Clarified encodings for pre emphasis pre tap and pre emphasis second post tap in Table 16 10 PMA Offsets and Values Clarified fact that you c...

Page 680: ...AP_USER for Arria V GZ and Stratix V devices Migrating from Stratix IV to Stratix V Devices March 2013 2 0 No changes from previous release Date Document Version Changes Made Introduction and Getting Started February 2013 1 9 Reformatted 10GBASE R PHY February 2013 1 9 Reformatted Corrected definition of the PLL type parameter Altera recommends the ATX PLL for data rates greater than 8 Gbps Backpl...

Page 681: ... PHY February 2013 1 9 Reformatted Low Latency PHY February 2013 1 9 Reformatted Deterministic Latency PHY February 2013 1 9 Reformatted Corrected headings in Table 11 4 The TX PMA Latency in UI and RX PMA Latency in UI were previously reversed In Table 11 3 added explanation of a latency uncertainty of 0 5 cycles when the byte serializer deserializer is turned on The location of the alignment pat...

Page 682: ...include constraints when CvP is enabled and frequency range for Arria V GZ and Cyclone V devices Corrected address for channel 2 in register based read examples Transceiver PHY Reset Controller February 2013 1 9 Reformatted Improved definition of pll_powerdown and rx_manualsignals Analog Parameters Set Using QSF Assignments February 2013 1 9 Reformatted Added the following settings to the Arria V ...

Page 683: ...elease 1G 10 Gbps Ethernet PHY November 2012 1 8 Initial release XAUI PHY November 2012 1 8 Added Arria V GZ support Moved Analog Options to a separate chapter Added constraint for tx_digitalreset when TX PCS uses bonded clocks Interlaken PHY November 2012 1 8 Added Arria V GZ support Added 12500 Mbps lane rate Moved Analog Options to a separate chapter Removed recommendation to use 40 for tx_user...

Page 684: ...ription of manual word alignment mode Low Latency PHY IP Core November 2012 1 8 Added Cyclone V support Moved Analog Options to a separate chapter Added constraint for tx_digitalreset when TX PCS uses bonded clocks Added RX bitslip option for the word aligner when the 10G PCS is selected Added description of reset_fine_control register at 0x044 This register is available when not using the embedde...

Page 685: ...abled if you must use the EyeQ monitor with a 1D eye Corrected definition of DFE_control bit at 0xa This register is write only Removed duty cycle calibration This function is run automati cally during the power on sequence Added DFE support including examples showing how to program this function Added DCD for Arria V devices Updated data for writes in Streamer Mode 1 Reconfiguration Changed data ...

Page 686: ... Stratix IV GX to Stratix IV GT This IP core only supports Stratix IV GT devices Added optional pll_locked status signal for Arria V and Stratix V devices Added optional rx_coreclkin Added arrows Transceiver Reconfiguration Controller IP Core connection to block diagram Changed the maximum frequency of phy_mgmt_clk to 150 MHz if the same clock is used for the Transceiver Reconfiguration Controller...

Page 687: ... Stratix V devices Interlaken PHY June 2012 1 7 Added support for custom user defined data rates Added the following QSF settings to all transceiver PHY XCVR_ TX_PRE_EMP_PRE_TAP_USER XCVR_TX_PRE_EMP_2ND_POST_TAP_ USER and 11 new settings for GT transceivers Changed the default value for XCVR_REFCLK_PIN_TERMINATION from DC_coupling_internal_100_Ohm to AC_coupling Updated the definition of tx_sync_d...

Page 688: ...nsceivers Added reference to Stratix V Transceiver Architecture chapter for detailed explanation of the PCS blocks Updated definition of rx_enapatternalign It is edge sensitive in most cases however if the PMA PCS interface width is 10 bits it is level sensitive Added definition for rx_byteordflag output status signal which is created when you enable the byte ordering block Changed the default val...

Page 689: ... for GT transceivers Added PLL reconfiguration option Changed the default value for XCVR_REFCLK_PIN_TERMINATION from DC_coupling_internal_100_Ohm to AC_coupling Removed references to the byte serializer and deserializer which is not included in the datapath Added GUI option for tx_clkout feedback path for TX PLL to align the TX and RX clock domains and figure illustrating this approach Added table...

Page 690: ...lk_powerdown 0x021 and pma_ tx_pll_is_locked 0x022 registers are only available when the Use external PMA control and reconfig option is turned On on the Additional Options tab of the GUI Clarified that the BER count functionality is for Stratix IV devices only Removed pma_rx_signaldetect register The 10GBASE R PHY does not support this functionality XAUI February 2012 1 5 Removed reset bits at re...

Page 691: ...me transceiver PHYs 10GBASE R December 2011 1 4 Removed description of calibration block powerdown register 0x021 which is not available for this transceiver PHY Changed definition of phy_mgmt_clk_reset This signal is active high and level sensitive XAUI December 2011 1 4 Changed definition of phy_mgmt_clk_reset This signal is active high and level sensitive Added Arria II GX to device support tab...

Page 692: ...f phy_mgmt_reset signal Should be phy_mgmt_ clk_reset Also a positive edge on this signal initiates a reset Added Enable Channel Interface parameter which is required for dynamic reconfiguration of transceivers Corrected formulas for signal width in top level signals figure Changed definition of phy_mgmt_clk_reset This signal is active high and level sensitive Deterministic Latency PHY December 20...

Page 693: ...et controller or user specified reset controller Updated directory names in simulation testbench 10GBASE R PHY Transceiver November 2011 1 3 Added support for Stratix V devices Added section discussing transceiver reconfiguration in Stratix V devices Removed rx_oc_busy signal which is included in the reconfigu ration bus Updated QSF settings to include text strings used to assign values and locati...

Page 694: ... 3 Added Arria V and Cyclone V support Addedbase data rate lane rate input clock frequency and PLL type parameters Revised reset options The 2 options for reset are now the embedded reset controller or a user specified reset logic Updated QSF settings to include text strings used to assign values and location of the assignment which is either a pin or PLL Low Latency PHY November 2011 1 3 Added ba...

Page 695: ...estrict this clock to 90 100 MHz Added column specifying availability of read and write access for PMA analog controls in the Transceiver Reconfiguration Controller IP Core chapter Renamed Avalon MM bus in for Transceiver Reconfiguration Controller reconfig_mgmt Provided frequency range for phy_mgmt_clk for the XAUI PHY IP Core in Arria II GX Cyclone IV GX HardCopy IV and Stratix IV GX devices Add...

Page 696: ...r Arria II GZ and HardCopy IV Added example testbench Renamed reconfig_fromgxb and reconfig_togxb reconfig_from_ xcvr and reconfig_to_xcvr respectively Updated definitions of rx_digital_reset and tx_digital_reset for the soft XAUI implementation in XAUI PHY IP Core Registers Changed description of rx_syncstatus register and signals to specify 2 bits per channel in hard XAUI and 1 bit per channel i...

Page 697: ...a Stratix V device Changed supported metaframe lengths from 1 8191 to 5 8191 Added pll_locked output port Added indirect_addr register at 0x080 for use in accessing PCS control and status registers Added new Bonded group size parameter PHY IP Core for PCI Express PHY PIPE May 2011 1 2 Renamed to PHY IP Core for PCI Express Moved dynamic reconfiguration for the transceiver outside of the PHY IP Cor...

Page 698: ... how to disable all word alignment functionality Low Latency PHY Transceiver May 2011 1 2 Moved dynamic reconfiguration for the transceiver outside of the Low Latency PHY IP Core The reconfiguration signals now connect to a separate Reconfiguration Controller IP Core Moved dynamics reconfiguration for the transceiver outside of the Custom PHY IP Core The reconfiguration signals now connect to a se...

Page 699: ...ces Removed table providing ordering codes for the Interlaken PHY IP Core Ordering codes are not required for Stratix V devices using the hard implementation of the Interlaken PHY Added note to 10GBASE R release information table stating that No ordering codes or license files are required for Stratix V devices Minor update to the steps to reconfigure a TX or RX PMA setting in the Transceiver Reco...

Page 700: ... to XAUI Top Level Signals Soft PCS and PMA and XAUI Top Level Signals Hard IP PCS and PMA as appropriate Changed register map to show word addresses instead of a byte offset from a base address Removed the rx_ctrldetect and rx_freqlocked signals Interlaken PHY Transceiver December 2010 1 1 Added simulation support in ModelSim SE Synopsys VCS MX Cadence NCSim Changed number of lanes supported from...

Page 701: ...al descrip tions Changed register map to show word addresses instead of a byte offset from a base address Low Latency PHY IP Core December 2010 1 1 Renamed management interface adding phy_ prefix Changed phy_mgmt_address from 16 to 9 bits Changed register map to show word addresses instead of a byte offset from a base address Removed rx_offset_cancellation_done signal Internal reset logic determin...

Page 702: ...t Altera This section provides the contact information for Altera Table 21 1 Altera Contact Information Contact 24 Contact Method Address Technical support Website www altera com support Technical training Website www altera com training Email custrain altera com Product literature Website www altera com literature Nontechnical support General Email nacomp altera com Software licensing Email autho...

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