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Altera Stratix IV GX Reference Manual Download Page 60

2–52

Chapter 2: Board Components

Memory

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

November 2010

Altera Corporation

DDR3 Top Port

The DDR3 top port consists of a single DDR3 devices, providing 128 Mbyte with a 
16-bit data bus. The board supports addressing for up to 4 times the memory if larger 
devices become available.

This memory interface is designed to run between 300 MHz, the minimum frequency 
for DDR3, and 533 MHz for a maximum theoretical bandwidth of over 68.2 Gbps. The 
internal bus in the FPGA is typically 2 or 4 times the width at full rate or half rate 
respectively. For example, a 533 MHz 64-bit interface will become a 267 MHz 256-bit 
bus.

Table 2–48

 lists the DDR3 top port pin assignments, signal names, and its functions. 

The signal names and types are relative to the Stratix IV device in terms of I/O setting 
and direction.

Table 2–48. DDR3 Top Port Pin Assignments, Signal Names and Functions (Part 1 of 2)

Board Reference

Description

Schematic Signal 

Name

I/O Standard

Stratix IV GX 

Device 

Pin Number

U14.T7

Address bus

DDR3TOP_A14

1.5-V SSTL Class I

B20

U14.T3

Address bus

DDR3TOP_A13

M22

U14.N7

Address bus

DDR3TOP_A12

A23

U14.R7

Address bus

DDR3TOP_A11

A19

U14.L7

Address bus

DDR3TOP_A10

B23

U14.R3

Address bus

DDR3TOP_A9

M21

U14.T8

Address bus

DDR3TOP_A8

F21

U14.R2

Address bus

DDR3TOP_A7

M20

U14.R8

Address bus

DDR3TOP_A6

G21

U14.P2

Address bus

DDR3TOP_A5

P19

U14.P8

Address bus

DDR3TOP_A4

D21

U14.N2

Address bus

DDR3TOP_A3

R20

U14.P3

Address bus

DDR3TOP_A2

N19

U14.P7

Address bus

DDR3TOP_A1

C22

U14.N3

Address bus

DDR3TOP_A0

D19

U14.M3

Bank address bus

DDR3TOP_BA2

A14

U14.N8

Bank address bus

DDR3TOP_BA1

E23

U14.M2

Bank address bus

DDR3TOP_BA0

B14

U14.J3

Row address select

DDR3TOP_RASn

A24

U14.K3

Column address select

DDR3TOP_CASn

B19

U14.L2

Chip select

DDR3TOP_CSn

D15

U14.L3

Write enable

DDR3TOP_WEn

C19

U14.K1

Termination enable

DDR3TOP_ODT

K15

U14.K9

Clock enable

DDR3TOP_CKE

A25

U14.J7

Clock P

DDR3TOP_CK_P

D24

U14.K7

Clock N

DDR3TOP_CK_N

C24

Summary of Contents for Stratix IV GX

Page 1: ...Innovation Drive San Jose CA 95134 www altera com MNL 01060 1 0 Reference Manual Stratix IV GX FPGA Development Board 530 Edition Subscribe Stratix IV GX FPGA Development Board 530 Edition Reference Manual ...

Page 2: ...a com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as ex...

Page 3: ...over External USB Blaster 2 16 Status Elements 2 16 Setup Elements 2 17 Board Settings DIP switch 2 18 JTAG Control DIP Switch 2 18 PCI Express Control DIP switch 2 19 Reset Configuration Push Button Switch 2 19 Rotary Switch 2 20 Clock Circuitry 2 21 Stratix IV GX FPGA Clock Inputs 2 22 Stratix IV GX FPGA Clock Outputs 2 25 General User Input Output 2 26 User Defined Push Button Switches 2 26 Use...

Page 4: ...vember 2010 Altera Corporation Power Supply 2 63 Power Distribution System 2 64 Power Measurement 2 65 Temperature Sense 2 66 Statement of China RoHS Compliance 2 67 Additional Information Document Revision History Info 1 How to Contact Altera Info 1 Typographic Conventions Info 1 ...

Page 5: ... cards available from both Altera and various partners f To see a list of the latest HSMC cards available or to download a copy of the HSMC specification refer to the Development Board Daughtercards page of the Altera website Design advancements and innovations such as the 8 5 Gbps transceiver modules the PCI Express hard IP implementation and programmable power technology ensure that designs impl...

Page 6: ...allel FPP configuration On Board USB BlasterTM for use with the Quartus II Programmer On Board Clocking Circuitry 50 MHz 125 MHz 155 52 MHz 156 25 MHz fixed frequency oscillators 100 MHz oscillator programmable to any frequency between 20 810 MHz 148 5 MHz voltage controlled crystal oscillator VCXO SMA connectors for external clock input SMA connector for clock output Memory devices 512 Mbyte DDR3...

Page 7: ...tches One user reset CPU Reset One configuration reset Three general user push button switches DIP Switches Eight user DIP switches Eight MAX II control DIP switches Power 16 V 20 V DC input PCI Express edge connector power On Board power measurement circuitry Mechanical PCI Express half length full height 6 6 x 4 376 PCI Express chassis or bench top operation ...

Page 8: ... damaged Therefore use anti static handling precautions when touching the board Figure 1 1 Stratix IV GX FPGA Development Board 530 Edition Block Diagram EP4SGX530KH40 Port A Port B 128 Mbytes DDR3 TOP 4 Mbytes QDRII TOP 0 4 Mbytes QDRII TOP 1 XCVR SMA OUT Buttons Switches LED CPLD 64 Mbytes FLASH 2 Mbytes SSRAM x8 Edge Oscillators 50 MHz 100 MHz 125 MHz 148 MHz 155 MHz 156 MHz 512 Mbytes DDR3 BOT...

Page 9: ...evelopment board reside in the Stratix IV GX development kit documents directory f For information about powering up the board and installing the demo software refer to the Stratix IV GX FPGA Development Kit 530 Edition User Guide This chapter consists of the following sections Board Overview Featured Device Stratix IV GX Device on page 2 5 MAX II CPLD EPM2210 System Controller on page 2 7 Configu...

Page 10: ... J11 Reset Configuration Push Button Switch S1 DDR3 x64 Bottom Port U5 U12 U18 U24 General User Push button Switches S3 S4 S5 Power Monitor Rotary Switch SW2 Power Switch SW1 User DIP Switch SW3 DC Input Jack J4 QDRII x18 x18 Top Port 1 U7 DDR3 x16 Top Port U14 QDRII x18 x18 Top Port 0 U22 JTAG Connector J8 PCI Express Edge Connector J17 EP4SGX530KH40C2N Table 2 1 Stratix IV GX FPGA Development Bo...

Page 11: ...0 MHz crystal oscillator for 10 Gigabit Ethernet or XAUI X3 148 M oscillator 148 500 MHz voltage controlled crystal oscillator for SDI Video X6 100 M oscillator 100 000 MHz programmable to any frequency between 20 810 MHz crystal oscillator for PCI Express or general use such as memories Multiplex with CLKIN_SMA_P based on CLK_SEL switch value X7 155 M oscillator 155 520 MHz crystal oscillator for...

Page 12: ...CMOS or 17 LVDS channels per the HSMC specification J7 USB Type B connector Embedded USB Blaster JTAG for programming the FPGA via a type B USB cable J6 Gigabit Ethernet port RJ 45 connector which provides a 10 100 1000 Ethernet connection via a Marvell 88E1111 PHY and the FPGA based Altera Triple Speed Ethernet MegaCore function in SGMII mode Video and Display Ports J11 HDMI video port 19 pin HDM...

Page 13: ...s of the Stratix IV GX EP4SGX530KH40 device Table 2 3 lists the Stratix IV GX component reference and manufacturing information Table 2 2 Stratix IV GX Device EP4SGX530KH40 Features ALMs Equivalent LEs M9K RAM Blocks M144K Blocks MLAB Blocks Total RAM Kbits 18 bit 18 bit Multipliers PLLs Transceivers 8 5 Gbps 3 2 Gbps Package Type 212 480 531 200 1 280 64 10 624 27 376 1 024 8 24 12 1517 pin FineL...

Page 14: ...ber of I Os Bank 3A 40 Bank 3B 24 Bank 3C 32 Bank 4C 32 Bank 4B 24 Bank 4A 40 4 4 Bank GXBL2 4 Bank GXBL1 Bank GXBL0 4 4 4 Bank GXBR2 Bank GXBR1 Bank GXBR0 Number of Transceiver Channel Table 2 4 Stratix IV GX Device Pin Count and Usage Part 1 of 2 Function I O Standard I O Count Special Pins DDR3 16 Top Port 1 5 V SSTL 49 2 Diff 8 DQS DDR3 64 Bottom Port 1 5 V SSTL 117 8 Diff 8 DQS QDRII Top Port...

Page 15: ...er The board utilizes the EPM2210 System Controller an Altera MAX II CPLD for the following purposes FPGA configuration from flash memory Power consumption monitoring Temperature monitoring Fan control Virtual JTAG interface for PC based power and temperature GUI Control registers for clocks Control registers for Remote System Update Control registers for SDI SRAM and fan speed Register with CPLD ...

Page 16: ... FPGA LTC2418 Controller FLASH Decoder Encoder GPIO JTAG Control SRAM Control Register Fast Configuration Downloader Si570 Programmable Oscillator Table 2 6 MAX II CPLD EPM2210 System Controller Device Pin Out Part 1 of 4 Schematic Signal Name I O Standard EPM2210 Pin Number EP4SGX230 Pin Number Description FSM_A25 2 5 V D5 AP30 FSM bus address FSM_A24 2 5 V B1 AN30 FSM bus address FSM_A23 2 5 V D...

Page 17: ... bus data FSM_D26 2 5 V P10 K31 FSM bus data FSM_D25 2 5 V R11 F31 FSM bus data FSM_D24 2 5 V N10 E31 FSM bus data FSM_D23 2 5 V T11 N29 FSM bus data FSM_D22 2 5 V M10 M29 FSM bus data FSM_D21 2 5 V T10 H31 FSM bus data FSM_D20 2 5 V P9 G31 FSM bus data FSM_D19 2 5 V R9 N30 FSM bus data FSM_D18 2 5 V T9 M30 FSM bus data FSM_D17 2 5 V T8 D33 FSM bus data FSM_D16 2 5 V N9 C33 FSM bus data FSM_D15 2 ...

Page 18: ...h address valid FPGA_CONFIG_D7 2 5 V D1 R34 FPGA configuration data FPGA_CONFIG_D6 2 5 V E5 R35 FPGA configuration data FPGA_CONFIG_D5 2 5 V D2 W26 FPGA configuration data FPGA_CONFIG_D4 2 5 V E4 V27 FPGA configuration data FPGA_CONFIG_D3 2 5 V C3 P34 FPGA configuration data FPGA_CONFIG_D2 2 5 V E3 N35 FPGA configuration data FPGA_CONFIG_D1 2 5 V C2 W29 FPGA configuration data FPGA_CONFIG_D0 2 5 V...

Page 19: ...N 2 5 V P7 DIP force fan on switch CLK_SEL 2 5 V T5 DIP clock select SMA or oscillator CLK_ENABLE 2 5 V N7 DIP clock oscillator enable PGM3 2 5 V J3 Rotary switch input PGM2 2 5 V K1 Rotary switch input PGM1 2 5 V J4 Rotary switch input PGM0 2 5 V J2 Rotary switch input RESET_CONFIGn 2 5 V K2 Force FPGA configuration push button switch CPU_RESETn 2 5 V M9 V34 Reset push button switch SRAM_MODE 2 5...

Page 20: ...e supplied USB cable Flash memory download is used for configuring the FPGA using stored images from the flash memory on either power up or pressing the reset configuration push button switch S1 External USB Blaster for configuring the FPGA using the external USB Blaster FPGA Programming over Embedded USB Blaster The USB Blaster is implemented using a type B USB connector J7 a FTDI USB 2 0 PHY dev...

Page 21: ...witch EPM2210 System Controller HSMC Port A HSMC Port B GPIO TMS GPIO TDO GPIO TDI JTAG Master GPIO DISABLE JTAG Master Slave JTAG Master Slave Installed HSMC Card Installed HSMC Card TCK TMS TDI TDO TCK TMS TDI TDO TCK TMS TDI TDO TCK TMS TDI TDO JTAG Slave JTAG Slave Analog Switch Analog Switch EPM2210_JTAG_EN HSMA_JTAG_EN HSMB_JTAG_EN ALWAYS ENABLED in chain SW6 1 SW6 2 SW6 3 SW4 2 10 pin JTAG ...

Page 22: ...e flash over the network The secondary method is to use the pre built PFL design included in the development kit The development board implements the Altera PFL megafunction for flash programming The PFL megafunction is a block of logic that is programmed into an Altera programmable logic device FPGA or CPLD The PFL functions as a utility for writing to a compatible flash device This pre built des...

Page 23: ...SH_D 15 0 FLASH_CEn FLASH_OEn FLASH_WEn FLASH_RSTn FLASH_ADVn MSEL 3 0 FPGA_nCONFIG FPGA_CONF_DONE FSM Bus Interface FLASH_RYBSYn Rotary Switch PGM 2 0 FPGA_nSTATUS USB_DISABLEn 2 5 V 10 kΩ 125 MHz 2 5 V FLASH_ADVn RESET_CONFIGn CONF_DONE_LED 2 5 V 10 kΩ FLASH_CLK FLASH_CLK FLASH_RSTn FLASH_RSTn 50 MHz CONFIG_CLK External JTAG Detect Table 2 8 Flash Memory Map Part 1 of 2 Name Size Kbyte Address U...

Page 24: ...vice on the JTAG chain f For more information on the following topics refer to the respective documents Board Update Portal refer to the Stratix IV GX FPGA Development Kit 530 Edition User Guide PFL design refer to the Stratix IV GX FPGA Development Kit 530 Edition User Guide PFL megafunction refer to AN 386 Using the Parallel Flash Loader with the Quartus II Software Status Elements The developme...

Page 25: ... Ethernet linked at 100 Mbps connection speed Driven by the Marvell 88E1111 PHY D32 1000 Green LED Illuminates to indicate Ethernet linked at 1000 Mbps connection speed Driven by the Marvell 88E1111 PHY D1 HSMC Port A Present Green LED Illuminates when the HSMC port A has a board or cable plugged in such that pin 160 becomes grounded Driven by the add in card D2 HSMC Port B Present Green LED Illum...

Page 26: ...N Embedded USB Blaster disabled OFF Embedded USB Blaster enabled OFF 3 LCD_PWRMON ON LCD driven from the Max II EPM2210 System Controller power monitor OFF LCD driven from the FPGA no power monitor ON 4 FAN_FORCE_ON ON Fan forced ON at full speed OFF Fan speed controlled by the MAX1619 device OFF 5 CLK_SEL ON 100 MHz oscillator input select OFF SMA input select ON 6 CLK_ENABLE ON On Board oscillat...

Page 27: ...h reserved for FPGA designs 3 HSMB_JTAG_EN ON Bypass HSMB OFF HSMB in chain ON 4 PCIE_JTAG_EN ON Bypass PCI Express OFF Reserved disables JTAG chain do not use ON Table 2 13 JTAG Control DIP Switch Controls Part 2 of 2 Switch Schematic Signal Name Description Default Table 2 14 JTAG Control DIP Switch Component Reference and Manufacturing Information Board Reference Device Description Manufacturer...

Page 28: ...Table 2 17 Reset Configuration Push Button Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturer Part Number Manufacturer Website S1 Push Button switch Panasonic Corporation EVQPAC07K www panasonic com Table 2 18 Power Rail Measurements Based on the Rotary Switch Position Part 1 of 2 Switch Schematic Signal Name Voltage V Device Pin Description 0 S...

Page 29: ...r DDR3BOT VCCIO_B4 Bank 4 I O power DDR3BOT E S4VCC_GXB 1 1 VCCR XCVR analog receive VCCT XCVR analog transmit VCCL_GXB XCVR clock distribution F 12 V 12 All 12 V power Table 2 18 Power Rail Measurements Based on the Rotary Switch Position Part 2 of 2 Switch Schematic Signal Name Voltage V Device Pin Description Table 2 19 Rotary Switch Component Reference and Manufacturing Information Board Refer...

Page 30: ...MA_CLK_IN0 2 5V NO OCT 2 5V NO OCT REFCLK INPUT SMA SMA LVPECL or Single Ended 2 to 4 buffer 100 M CLK_SEL CLKINRT_100_P CLKINLT_100_P CLKINTOP_100_P CLKINBOT_100_P DIPSW SW4 5 To REFCLK Clock Inputs CLK1p CLK0p CLK9p CLK8p CLK10p CLK11p CLK7p CLK6p CLK4p CLK5p CLK13p CLK12p CLK14p CLK15p PLL B2 PLL B1 PLL T2 PLL T1 PLL L3 PLL L4 PLL L1 PLL L2 PLL R3 PLL R4 PLL R1 PLL R2 HSMA_CLK_IN_P2 LVDS OCT 10...

Page 31: ... SMA LVPECL or Single Ended 2 to 4 buffer 100 M CLK_SEL CLKINTOP_100_P CLKINBOT_100_P CLKINRT_100_P CLKINLT_100_P DIPSW SW4 5 To GPLL Clock Inputs Right Edge REFCLK Inputs Left Edge REFCLK Inputs The 100 MHz oscillator X6 can be programmed to any frequency between 20 MHz and 810 MHz but powers up to 100 MHz using the clock control GUI installed with the kit CD Table 2 20 Stratix IV GX FPGA Develop...

Page 32: ...r U50 and LVDS to the transceiver QR2 REFCLK input CLKINLT_100_N G39 Samtec HSMC HSMA_CLK_IN0 AB34 LVTTL Single ended input from the installed HSMC cable or board Samtec HSMC HSMA_CLK_IN_P1 AC6 LVDS or LVTTL LVDS input from the installed HSMC cable or board Can also support two LVTTL inputs HSMA_CLK_IN_N1 AC5 Samtec HSMC HSMA_CLK_IN_P2 AF6 LVDS or LVTTL LVDS input from the installed HSMC cable or ...

Page 33: ...CLK_OUT_P2 LVDS NO OCT DDR3BOT_CK_P SSTL 15 Class I DDR3BOT_CK_N SSTL 15 Class I DDR3TOP_CK_P SSTL 15 Class I 50 Ω OCT DDR3TOP_CK_N SSTL 15 Class I 50 Ω OCT QDR2_TOP0_K_P 1 5V HSTL Class I 50 Ω OCT QDR2_TOP0_K_N 1 5V HSTL Class I 50 Ω OCT QDR2_TOP1_K_P 1 5V HSTL Class I 50 Ω OCT QDR2_TOP1_K_N 1 5V HSTL Class I 50 Ω OCT Table 2 21 Stratix IV GX FPGA Development Board 530 Edition Clock Outputs Part ...

Page 34: ...for these general user push button switches Samtec HSMC HSMB_CLK_OUT_P1 K8 LVDS or 2 5 V LVDS output or two 2 5 V CMOS outputs HSMB_CLK_OUT_N1 J8 Samtec HSMC HSMB_CLK_OUT_P2 K10 LVDS or 2 5 V LVDS output Can also support two CMOS outputs HSMB_CLK_OUT_N3 J10 Table 2 21 Stratix IV GX FPGA Development Board 530 Edition Clock Outputs Part 2 of 2 Connector Schematic Signal Name Pin I O Standard Descrip...

Page 35: ...ional FPGA input control There is no board specific function for these switches Table 2 25 lists the user defined DIP switch schematic signal names and their corresponding Stratix IV GX pin numbers Table 2 23 User Defined Push Button Switch Schematic Signal Names and Functions Board Reference Description Schematic Signal Name I O Standard Stratix IV GX Device Pin Number S2 User Defined push button...

Page 36: ...re is no board specific function for these LEDs Table 2 27 lists the user defined LED schematic signal names and their corresponding Stratix IV GX pin numbers Table 2 26 User Defined DIP Switch Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturer Part Number Manufacturer Website SW3 Eight Position DIP switch C K Components TDA08H0SB1 www ck compon...

Page 37: ... directly to the board s 14 pin header so it can be easily removed for access to components under the display You can also use the header for debugging or other purposes Table 2 28 User Defined LED Component Reference and Manufacturing Information Board Reference Device Description Manufacturer Manufacturer Part Number Manufacturer Website D6 to D13 D16 to D23 Green LEDs 1206 SMT Clear Lens 2 1 V ...

Page 38: ...ions Board Reference Description Schematic Signal Name I O Standard Stratix IV GX Device Pin Number J16 7 LCD data bus LCD_DATA0 2 5 V AD31 J16 8 LCD data bus LCD_DATA1 AJ34 J16 9 LCD data bus LCD_DATA2 R31 J16 10 LCD data bus LCD_DATA3 L32 J16 11 LCD data bus LCD_DATA4 T30 J16 12 LCD data bus LCD_DATA5 AN34 J16 13 LCD data bus LCD_DATA6 T31 J16 14 LCD data bus LCD_DATA7 AD30 J16 4 LCD data or com...

Page 39: ...Gbps lane to Gen2 at 5 0 Gbps lane for a maximum of 40 Gbps full duplex The power for the board can be sourced entirely from the PCI Express edge connector when installed into a PC motherboard Although the board can also be powered by a laptop power supply for use on a lab bench it is not recommended to power from both supplies at the same time Ideal diode power sharing devices have been designed ...

Page 40: ...ard Reference Description Schematic Signal Name I O Standard Stratix IV GX Device Pin Number J17 A47 Add in card transmit bus PCIE_TX_P7 1 4 V PCML P36 J17 A48 Add in card transmit bus PCIE_TX_N7 P37 J17 A43 Add in card transmit bus PCIE_TX_P6 T36 J17 A44 Add in card transmit bus PCIE_TX_N6 T37 J17 A39 Add in card transmit bus PCIE_TX_P5 AB36 J17 A40 Add in card transmit bus PCIE_TX_N5 AB37 J17 A3...

Page 41: ...t traffic J17 B38 Add in card receive bus PCIE_RX_N5 1 4 V PCML AC39 J17 B33 Add in card receive bus PCIE_RX_P4 AE38 J17 B34 Add in card receive bus PCIE_RX_N4 AE39 J17 B27 Add in card receive bus PCIE_RX_P3 AG38 J17 B28 Add in card receive bus PCIE_RX_N3 AG39 J17 B23 Add in card receive bus PCIE_RX_P2 AJ38 J17 B24 Add in card receive bus PCIE_RX_N2 AJ39 J17 B19 Add in card receive bus PCIE_RX_P1 ...

Page 42: ...BASE TX 1000BASE T Table 2 35 Ethernet PHY Pin Assignments Signal Names and Functions Board Reference Description Schematic Signal Name I O Standard Stratix IV GX Device Pin Number U21 82 SGMII TX data ENET_TX_P LVDS L29 U21 81 SGMII TX data ENET_TX_N K29 U21 77 SGMII RX data ENET_RX_P AC31 U21 75 SGMII RX data ENET_RX_N AC32 U21 25 Management bus control ENET_MDC 2 5 V AH34 U21 24 Management bus ...

Page 43: ...f signal and power pins acting both as a shield and a reference The HSMC host connector is based on the 0 5 mm pitch QSH QTH family of high speed board to board connectors from Samtec There are three banks in this connector Bank 1 has every third pin removed as done in the QSH DP QTH DP series Bank 2 and bank 3 have all the pins populated as done in the QSH QTH series Figure 2 11 shows the bank ar...

Page 44: ...MA_TX_P5 AB4 J1 10 Transceiver RX bit 5 HSMA_RX_P5 AC2 J1 11 Transceiver TX bit 5n HSMA_TX_N5 AB3 J1 12 Transceiver RX bit 5n HSMA_RX_N5 AC1 J1 13 Transceiver TX bit 4 HSMA_TX_P4 AD4 J1 14 Transceiver RX bit 4 HSMA_RX_P4 AE2 J1 15 Transceiver TX bit 4n HSMA_TX_N4 AD3 J1 16 Transceiver RX bit 4n HSMA_RX_N4 AE1 J1 17 Transceiver TX bit 3 HSMA_TX_P3 AF4 J1 18 Transceiver RX bit 3 HSMA_RX_P3 AG2 J1 19...

Page 45: ...1n or CMOS bit 10 HSMA_TX_D_N1 AP7 J1 56 LVDS RX bit 1n or CMOS bit 11 HSMA_RX_D_N1 AU8 J1 59 LVDS TX bit 2 or CMOS bit 12 HSMA_TX_D_P2 AE13 J1 60 LVDS RX bit 2 or CMOS bit 13 HSMA_RX_D_P2 AP8 J1 61 LVDS TX bit 2n or CMOS bit 14 HSMA_TX_D_N2 AE12 J1 62 LVDS RX bit 2n or CMOS bit 15 HSMA_RX_D_N2 AR8 J1 65 LVDS TX bit 3 or CMOS bit 16 HSMA_TX_D_P3 AL8 J1 66 LVDS RX bit 3 or CMOS bit 17 HSMA_RX_D_P3 ...

Page 46: ... bit 9n or CMOS bit 47 HSMA_RX_D_N9 AN5 J1 113 LVDS TX bit 10 or CMOS bit 48 HSMA_TX_D_P10 AF11 J1 114 LVDS RX bit 10 or CMOS bit 49 HSMA_RX_D_P10 AM6 J1 115 LVDS TX bit 10n or CMOS bit 50 HSMA_TX_D_N10 AF10 J1 116 LVDS RX bit 10n or CMOS bit 51 HSMA_RX_D_N10 AM5 J1 119 LVDS TX bit 11 or CMOS bit 52 HSMA_TX_D_P11 AD10 J1 120 LVDS RX bit 11 or CMOS bit 53 HSMA_RX_D_P11 AL6 J1 121 LVDS TX bit 11n or...

Page 47: ..._N2 AE5 J1 160 HSMC Port A presence detect HSMA_PRSNTn 2 5 V AG12 D4 User LED to show RX data activity on HSMC Port A HSMA_RX_LED D5 D3 User LED to show TX data activity on HSMC Port A HSMA_TX_LED C6 Table 2 37 HSMC Port A Pin Assignments Schematic Signal Names and Functions Part 4 of 4 Board Reference Description Schematic Signal Name I O Standard Stratix IV GX Device Pin Number Table 2 38 HSMC P...

Page 48: ... AF29 J2 34 Management serial clock HSMB_SCL AB27 J2 35 JTAG clock signal FPGA_JTAG_TCK J2 36 JTAG mode select signal FPGA_JTAG_TMS J2 37 JTAG data output HSMB_JTAG_TDO J2 38 JTAG data input HSMB_JTAG_TDI J2 39 Dedicated CMOS clock out HSMB_CLK_OUT0 AK29 J2 40 Dedicated CMOS clock in HSMB_CLK_IN0 AA35 J2 41 Dedicated CMOS I O bit 0 HSMB_D0 AP10 J2 42 Dedicated CMOS I O bit 1 HSMB_D1 AN10 J2 43 Ded...

Page 49: ...X_D_N6 P8 J2 86 LVDS RX bit 6n or CMOS bit 31 HSMB_RX_D_N6 L5 J2 89 LVDS TX bit 7 or CMOS bit 32 HSMB_TX_D_P7 N11 J2 90 LVDS RX bit 7 or CMOS bit 33 HSMB_RX_D_P7 K6 J2 91 LVDS TX bit 7n or CMOS bit 34 HSMB_TX_D_N7 N10 J2 92 LVDS RX bit 7n or CMOS bit 35 HSMB_RX_D_N7 K5 J2 95 LVDS or CMOS clock out 1 or CMOS bit 36 HSMB_CLK_OUT_P1 K8 J2 96 LVDS or CMOS clock in 1 or CMOS bit 37 HSMB_CLK_IN_P1 AB6 J...

Page 50: ...J2 139 LVDS TX bit 14n or CMOS bit 66 HSMB_TX_D_N14 R11 J2 140 LVDS RX bit 14n or CMOS bit 67 HSMB_RX_D_N14 C7 J2 143 LVDS TX bit 15 or CMOS bit 68 HSMB_TX_D_P15 T13 J2 144 LVDS RX bit 15 or CMOS bit 69 HSMB_RX_D_P15 D8 J2 145 LVDS TX bit 15n or CMOS bit 70 HSMB_TX_D_N15 T12 J2 146 LVDS RX bit 15n or CMOS bit 71 HSMB_RX_D_N15 C8 J2 149 LVDS TX bit 16 or CMOS bit 72 HSMB_TX_D_P16 R13 J2 150 LVDS RX...

Page 51: ...omatic input video format timing detection CEA 861B circuit On the digital audio aspect this device supports standard S PDIF for stereo LPCM or compressed audio of up to 192 kHz This device also supports 8 channel uncompressed LPCM I2S audio of up to 192 kHz No audio master clock is needed for supporting S PDIF and I2S This device supports an on chip microcontroller MCU with I2C master to perform ...

Page 52: ...CP EDID Microcontroller Interrupt Handler AD9889B SCL SDA MCL MDA INT HPD DDCSDA DDCSCL Tx0 Tx0 Tx1 Tx1 Tx2 Tx2 TxC TxC SCLK LRCLK MCLK S PDIF D 23 0 DE HSYNC VSYNC CLK I2S 3 0 Table 2 40 HDMI Video Output Pin Assignments Schematic Signal Names and Functions Part 1 of 2 Board Reference Description Schematic Signal Name I O Standard Stratix IV GX Device Pin Number U25 B1 Video data bus HDMI_D0 1 8 ...

Page 53: ...data bus DE HDMI_DE AK27 U25 C1 Video data bus HSYNC HDMI_HSYNC AE24 U25 D2 Video data bus VSYNC HDMI_VSYNC AE25 U25 E2 Audio SPDIF data HDMI_SPDIF AR28 U25 E1 Audio SPDIF clock HDMI_MCLK AP28 U25 F2 Audio I2S bus HDMI_I2S0 AT29 U25 F1 Audio I2S bus HDMI_I2S1 AU29 U25 G2 Audio I2S bus HDMI_I2S2 AU28 U25 G1 Audio I2S bus HDMI_I2S3 AT28 U25 H2 Audio I2S bus clock HDMI_SCLK AH24 U25 H1 Audio LR clock...

Page 54: ...0 ppm using the UP and DN voltage control lines to the VCXO Table 2 42 shows the supported output standards for the SD and HD input Table 2 43 summarizes the SDI video output interface pin assignments The signal names and directions are relative to the Stratix IV GX FPGA Figure 2 13 shows the SDI cable driver Table 2 42 Supported Output Standards for SD and HD Input SD_HD Input Supported Output St...

Page 55: ...the SDI cable equalizer Table 2 44 SDI Cable Equalizer Lengths Data Rate Mbps Cable Type Maximum Cable Length m 270 Belden 1694A 400 1485 140 2970 120 Table 2 45 SDI Video Input Interface Pin Assignments Schematic Signal Names and Functions Board Reference Description Schematic Signal Name I O Standard MAX II CPLD EPM2210 System Controller Pin Number Stratix IV GX Device Pin Number U2 11 SDI video...

Page 56: ... or 4 times the width at full rate or half rate respectively For example a 533 MHz 64 bit interface will become a 267 MHz 256 bit bus Table 2 46 lists the DDR3 DIMM pin assignments signal names and functions The signal names and types are relative to the Stratix IV device in terms of I O setting and direction Table 2 46 DDR3 Bottom Port Pin Assignments Schematic Signal Names and Functions Part 1 o...

Page 57: ...F2 Data bus byte lane 0 DDR3BOT_DQ2 AN14 U5 F8 Data bus byte lane 0 DDR3BOT_DQ3 AL14 U5 H3 Data bus byte lane 0 DDR3BOT_DQ4 AR14 U5 H8 Data bus byte lane 0 DDR3BOT_DQ5 AN13 U5 G2 Data bus byte lane 0 DDR3BOT_DQ6 AP14 U5 H7 Data bus byte lane 0 DDR3BOT_DQ7 AP13 U5 E7 Write mask byte lane 0 DDR3BOT_DM0 AL13 U5 F3 Data strobe P byte lane 0 DDR3BOT_DQS_P0 AR13 U5 G3 Data strobe N byte lane 0 DDR3BOT_D...

Page 58: ...ask byte lane 3 DDR3BOT_DM3 AF17 U12 C7 Data strobe P byte lane 3 DDR3BOT_DQS_P3 AK16 U12 B7 Data strobe N byte lane 3 DDR3BOT_DQS_N3 AL16 U18 E3 Data bus byte lane 4 DDR3BOT_DQ32 AU23 U18 F7 Data bus byte lane 4 DDR3BOT_DQ33 AN23 U18 F2 Data bus byte lane 4 DDR3BOT_DQ34 AT23 U18 F8 Data bus byte lane 4 DDR3BOT_DQ35 AM23 U18 H3 Data bus byte lane 4 DDR3BOT_DQ36 AP23 U18 H8 Data bus byte lane 4 DDR...

Page 59: ...24 F3 Data strobe P byte lane 6 DDR3BOT_DQS_P6 AT26 U24 G3 Data strobe N byte lane 6 DDR3BOT_DQS_N6 AU26 U24 D7 Data bus byte lane 7 DDR3BOT_DQ56 AJ23 U24 C3 Data bus byte lane 7 DDR3BOT_DQ57 AK24 U24 C8 Data bus byte lane 7 DDR3BOT_DQ58 AF23 U24 C2 Data bus byte lane 7 DDR3BOT_DQ59 AH23 U24 A7 Data bus byte lane 7 DDR3BOT_DQ60 AG22 U24 A2 Data bus byte lane 7 DDR3BOT_DQ61 AJ22 U24 B8 Data bus byt...

Page 60: ...ents Signal Names and Functions Part 1 of 2 Board Reference Description Schematic Signal Name I O Standard Stratix IV GX Device Pin Number U14 T7 Address bus DDR3TOP_A14 1 5 V SSTL Class I B20 U14 T3 Address bus DDR3TOP_A13 M22 U14 N7 Address bus DDR3TOP_A12 A23 U14 R7 Address bus DDR3TOP_A11 A19 U14 L7 Address bus DDR3TOP_A10 B23 U14 R3 Address bus DDR3TOP_A9 M21 U14 T8 Address bus DDR3TOP_A8 F21...

Page 61: ... H8 Data bus byte lane 0 DDR3TOP_DQ5 C13 U14 G2 Data bus byte lane 0 DDR3TOP_DQ6 A11 U14 H7 Data bus byte lane 0 DDR3TOP_DQ7 B13 U14 E7 Write mask byte lane 0 DDR3TOP_DM0 B11 U14 F3 Data strobe P byte lane 0 DDR3TOP_DQS_P0 D14 U14 G3 Data strobe N byte lane 0 DDR3TOP_DQS_N0 C14 U14 D7 Data bus byte lane 1 DDR3TOP_DQ8 K22 U14 C3 Data bus byte lane 1 DDR3TOP_DQ9 D22 U14 C8 Data bus byte lane 1 DDR3T...

Page 62: ...R24 U22 P7 Address bus QDR2TOP0_A11 N20 U22 P5 Address bus QDR2TOP0_A10 A31 U22 P4 Address bus QDR2TOP0_A9 A29 U22 N7 Address bus QDR2TOP0_A8 P20 U22 N6 Address bus QDR2TOP0_A7 B31 U22 N5 Address bus QDR2TOP0_A6 B29 U22 C7 Address bus QDR2TOP0_A5 D27 U22 C5 Address bus QDR2TOP0_A4 F26 U22 B8 Address bus QDR2TOP0_A3 A27 U22 B4 Address bus QDR2TOP0_A2 G26 U22 R8 Address bus QDR2TOP0_A1 P24 U22 R9 Ad...

Page 63: ... Read data bus QDR2TOP0_Q13 G27 U22 F2 Read data bus QDR2TOP0_Q12 F27 U22 E3 Read data bus QDR2TOP0_Q11 D28 U22 D3 Read data bus QDR2TOP0_Q10 E28 U22 B2 Read data bus QDR2TOP0_Q9 D29 U22 B11 Read data bus QDR2TOP0_Q8 E29 U22 C10 Read data bus QDR2TOP0_Q7 F28 U22 E11 Read data bus QDR2TOP0_Q6 G29 U22 F11 Read data bus QDR2TOP0_Q5 J26 U22 J10 Read data bus QDR2TOP0_Q4 K26 U22 K11 Read data bus QDR2T...

Page 64: ...ting and direction Table 2 51 QDRII Top Port 0 Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Website U22 QDRII 4 M 18 400 MHZ Cypress CY7C2563KV18 400BZXC www cypress com NEC uPD44647186AF5 E22 FQ1 www nec com Table 2 52 QDRII Top Port 1 Pin Assignments Schematic Signal Names and Functions Part 1 of 3 Board Referen...

Page 65: ...11 Write data bus QDR2TOP1_D2 N17 U7 N11 Write data bus QDR2TOP1_D1 M17 U7 P10 Write data bus QDR2TOP1_D0 P16 U7 B6 Write clock P QDR2TOP1_K_P N16 U7 A6 Write clock N QDR2TOP1_K_N M16 U7 A4 Write port select QDR2TOP1_WPSn D18 U7 B7 Write byte write select 0 QDR2TOP1_BWSn0 H17 U7 A5 Write byte write select 1 QDR2TOP1_BWSn1 J17 U7 R6 Termination enable QDR2TOP1_ODT C20 U7 P3 Read data bus QDR2TOP1_Q...

Page 66: ... 10 ns and at 50 MHz the latency is 40 ns The write latency is one clock U7 F11 Read data bus QDR2TOP1_Q5 1 5 V HSTL Class I G14 U7 J10 Read data bus QDR2TOP1_Q4 H14 U7 K11 Read data bus QDR2TOP1_Q3 K12 U7 L11 Read data bus QDR2TOP1_Q2 J12 U7 M10 Read data bus QDR2TOP1_Q1 K13 U7 P11 Read data bus QDR2TOP1_Q0 J13 U7 A11 Read clock P QDR2TOP1_CQ_P H13 U7 A1 Read clock N QDR2TOP1_CQ_N L13 U7 A8 Read ...

Page 67: ...FSM_A21 AR32 U30 R11 Address bus FSM_A20 AP32 U30 R10 Address bus FSM_A19 AH29 U30 R9 Address bus FSM_A18 AG29 U30 R8 Address bus FSM_A17 AR35 U30 R4 Address bus FSM_A16 AP35 U30 R3 Address bus FSM_A15 AL32 U30 P11 Address bus FSM_A14 AK32 U30 P10 Address bus FSM_A13 AU33 U30 P9 Address bus FSM_A12 AT33 U30 P8 Address bus FSM_A11 AH30 U30 P4 Address bus FSM_A10 AJ31 U30 P3 Address bus FSM_A9 AR34 ...

Page 68: ... D34 U30 J10 Data bus FSM_D0 C34 U30 N11 Data bus parity byte lane 0 SRAM_DQP0 F35 U30 C11 Data bus parity byte lane 1 SRAM_DQP1 AJ32 U30 C1 Data bus parity byte lane 2 SRAM_DQP2 N33 U30 N1 Data bus parity byte lane 3 SRAM_DQP3 AJ35 U30 B6 Clock SRAM_CLK AE26 U30 B8 Output enable SRAM_OEn AK34 U30 A3 Chip enable SRAM_CEn AT30 U30 B5 Byte lane 0 write enable SRAM_BWn0 AH27 U30 A5 Byte lane 1 write ...

Page 69: ...es and functions The signal names and types are relative to the Stratix IV GX device in terms of I O setting and direction U30 R1 Mode SRAM_MODE 2 5 V Connects to the MAX II CPLD EPM2210 System Controller U30 H11 Sleep SRAM_ZZ AJ29 Table 2 54 SSRAM Pin Assignments Schematic Signal Names and Functions Part 3 of 3 Board Reference Description Schematic Signal Name I O Standard Stratix IV GX Device Pi...

Page 70: ...A2 AC26 U32 A1 Address bus FSM_A1 AP33 U32 E7 Data bus FSM_D16 C33 U32 G7 Data bus FSM_D15 N31 U32 H5 Data bus FSM_D14 M31 U32 F5 Data bus FSM_D13 C32 U32 F4 Data bus FSM_D12 B32 U32 F3 Data bus FSM_D11 J32 U32 E3 Data bus FSM_D10 H32 U32 E1 Data bus FSM_D9 D35 U32 H7 Data bus FSM_D8 C35 U32 G6 Data bus FSM_D7 N28 U32 G5 Data bus FSM_D6 M28 U32 E5 Data bus FSM_D5 D31 U32 E4 Data bus FSM_D4 C31 U32...

Page 71: ...ors An on board multi channel analog to digital converter ADC is used to measure both the voltage and current for several specific board rails The power utilization is displayed in a GUI that graphs power consumption versus time U32 F6 Address valid FLASH_ADVn 2 5 V AN31 U32 F7 Ready FLASH_RDYBSYn AT32 Table 2 56 Flash Pin Assignments Schematic Signal Names and Functions Part 3 of 3 Board Referenc...

Page 72: ...scillators 2 5 V 0 484 A 2 5 V 0 181 A 2 5 V 0 181 A 2 5 V 0 050 A 3 3V_PCIe 0 69 A 4 77 A with full HSMCs 3 3V HSMC Port A and B SDI ICS 8543 LVDS Clock Buffer 3 3 V 4 050 A LT3025 1 Linear S4VCCAUX S4 VCCAUX 2 5 V 0 250 A S4VCCA_GXB S4 Transceiver VCCA 3 0 V 0 331 A S4VCCIO_B7B8 S4 Bank 7 8 VCCIO S4VCCIO_B3B4 S4 Bank 3 4 VCCIO 1 5 V 0 880 A 1 5 V 0 410 A R220 14 V 20 V DC INPUT 5 75 A 4 77 A LT3...

Page 73: ...o the rail If no subnet is named the power is the total output power for that voltage Figure 2 16 Power Measurement Circuit SCK DSI DSO CSn 8 Ch To Plane 0x0 To Plane 0xE Supply 0x0 Supply 0xE R SENSE R SENSE SCK DSI DSO CSn 8 Ch EPM2210 EP4SGX530 LTC2418 LTC2418 U1 EPM 240 USB PHY To User PC Power GUI JTAG Chain SPI Bus Embedded USB Blaster To Plane 0xF 12 V Supply R SENSE SCL SDA 1 Ch LTC4151 SM...

Page 74: ...M2210 System Controller source code found in the development board installation directory install dir stratixIVGX_4sgx530_fpga examples max2 f For more information on the development board installation directory refer to the Stratix IV GX FPGA Development Kit 530 Edition User Guide 6 S4VCCPT 1 5 VCCPT Programmable power tech 7 S4VCCD_PLL 0 9 VCCD_PLL PLL digital 8 S4VCCA_GXB 3 0 VCCA XCVR analog T...

Page 75: ...SENSE_SMB_DATA R4 AH32 U27 9 Programmable over temperature OVERTEMPn P5 U27 11 Programmable alert TSENSE_ALERTn M2 Table 2 61 Temperature Sense Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Website U26 Temperature sense remote and local programmable alert Maxim MAX1619MEE T www maxim ic com Table 2 62 Table of Haza...

Page 76: ...2 68 Chapter 2 Board Components Statement of China RoHS Compliance Stratix IV GX FPGA Development Board 530 Edition Reference Manual November 2010 Altera Corporation ...

Page 77: ...on technical support General Email nacomp altera com Software Licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Visual Cue Meaning Bold Type with Initial Capital Letters Indicate command names dialog box titles dialog box options and other GUI labels For example Save As dialog box For GUI elements capitalization mat...

Page 78: ... SUBDESIGN and logic function names for example TRI r An angled arrow instructs you to press the Enter key 1 2 3 and a b c and so on Numbered steps indicate a list of items when the sequence of the items is important such as the steps listed in a procedure Bullets indicate a list of items when the sequence of the items is not important 1 The hand points to information that requires special attenti...

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