Transmit Descriptor
The application software must program the control bits TDES0[31:18] during the transmit descriptor
initialization. When the DMA updates the descriptor, it writes back all the control bits except the OWN bit
(which it clears) and updates the status bits[7:0].
With the advance timestamp support, the snapshot of the timestamp to be taken can be enabled for a given
frame by setting Bit 25 (TTSE) of TDES0. When the descriptor is closed (that is, when the OWN bit is
cleared), the timestamp is written into TDES6 and TDES7. This is indicated by the status Bit 17 (TTSS) of
TDES0.
When advanced timestamp feature is enabled, the software should set Bit 7 of Register 0 (Bus Mode
Register), so that the DMA operates with extended descriptor size. When this control bit is reset, the
TDES4-TDES7 descriptor space is not valid.
†
Note:
Figure 17-11: Transmit Descriptor Fields - Format
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TDES0
O
W
N
Ctrl [30:26]
T
T
S
E
Ctrl [24:18]
T
T
S
S
Status [16:7]
Ctrl/Status
[6:3]
Status
[2:0]
TDES1
Ctrl
[31:29]
Buffer 2 Byte Count [28:16]
RES
Buffer 1 Byte Count [12:0]
]
0
:
1
3
[
s
s
e
r
d
d
A
1
r
e
ff
u
B
2
S
E
D
T
]
0
:
1
3
[
s
s
e
r
d
d
A
r
o
t
p
ir
c
s
e
D
t
x
e
N
r
o
]
0
:
1
3
[
s
s
e
r
d
d
A
2
r
e
ff
u
B
3
S
E
D
T
d
e
v
r
e
s
e
R
4
S
E
D
T
d
e
v
r
e
s
e
R
5
S
E
D
T
]
0
:
1
3
[
w
o
L
p
m
a
t
s
e
m
i
T
ti
m
s
n
a
r
T
6
S
E
D
T
]
0
:
1
3
[
h
g
i
H
p
m
a
t
s
e
m
i
T
ti
m
s
n
a
r
T
7
S
E
D
T
The DMA always reads or fetches four DWORDS of the descriptor from system memory to obtain the buffer
and control information.
†
Altera Corporation
Ethernet Media Access Controller
17-37
Transmit Descriptor
cv_54017
2013.12.30
