Altera Cyclone V GX FPGA Page 33 Reference Manual Download

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Chapter 2: Board Components

2–25

Components and Interfaces

May 2013

Altera Corporation

Cyclone V GX FPGA Development Board

Reference Manual

Figure 2–6

shows the PCI Express reference clock levels.

The JTAG and SMB are optional signals in the PCI Express specification. Both types of
signals are wired to the Cyclone V GX but are not required for normal operation.

Table 2–22

summarizes the PCI Express pin assignments. The signal names and

directions are relative to the Cyclone V GX.

Figure 2–6. PCI Express Reference Clock Levels

MAX

= 1.15 V

CROSS MAX

= 550 mV

CROSS MIN

= 250 mV

MIN

= –0.30 V

REFCLK –

Table 2–22. PCI Express Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (J19)

Schematic Signal Name

Cyclone V GX

Pin Number

I/O Standard

Description

PCIE_JTAG_TCK

—

LVTTL

JTAG chain clock

PCIE_JTAG_TDI

—

LVTTL

JTAG chain data in

PCIE_JTAG_TDO

—

LVTTL

JTAG chain data out

PCIE_JTAG_TMS

—

LVTTL

JTAG chain mode select

A11

PCIE_PERSTN

W27

LVTTL

Reset

PCIE_PRSNT1N

—

LVTTL

Link width DIP switch

B17

PCIE_PRSNT2N_X1

—

LVTTL

Hot plug present detect

B31

PCIE_PRSNT2N_X4

—

LVTTL

Hot plug present detect

A13

PCIE_REFCLK_P

HCSL

Reference clock input

A14

PCIE_REFCLK_N

HCSL

Reference clock input

B14

PCIE_RX_P0

AG2

1.5-V PCML

Receive bus

B15

PCIE_RX_N0

AG1

1.5-V PCML

Receive bus

B19

PCIE_RX_P1

AE2

1.5-V PCML

Receive bus

B20

PCIE_RX_N1

AE1

1.5-V PCML

Receive bus

B23

PCIE_RX_P2

AC2

1.5-V PCML

Receive bus

B24

PCIE_RX_N2

AC1

1.5-V PCML

Receive bus

B27

PCIE_RX_P3

AA2

1.5-V PCML

Receive bus

B28

PCIE_RX_N3

AA1

1.5-V PCML

Receive bus

PCIE_SMBCLK

R11

2.5-V

SMB clock

PCIE_SMBDAT

V22

2.5-V

SMB data

A16

PCIE_TX_P0

AF4

1.5-V PCML

Transmit bus

A17

PCIE_TX_N0

AF3

1.5-V PCML

Transmit bus

A21

PCIE_TX_P1

AD4

1.5-V PCML

Transmit bus

A22

PCIE_TX_N1

AD3

1.5-V PCML

Transmit bus

Summary of Contents for Cyclone V GX FPGA

Page 1: ...101 Innovation Drive San Jose CA 95134 www altera com MNL 01072 1 2 Reference Manual Cyclone V GX FPGA Development Board Feedback Subscribe Cyclone V GX FPGA Development Board Reference Manual ...

Page 2: ...or products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to...

Page 3: ...Board Settings DIP Switch 2 16 JTAG Chain Control DIP Switch 2 16 PCI Express Link Width DIP Switch 2 17 CPU Reset Push Button 2 17 MAX V Reset Push Button 2 17 Program Configuration Push Button 2 17 Program Select Push Button 2 17 Clock Circuitry 2 18 On Board Oscillators 2 18 Off Board Clock Input Output 2 19 General User Input Output 2 20 User Defined Push Buttons 2 20 User Defined DIP Switch 2...

Page 4: ...ent Board May 2013 Altera Corporation Reference Manual Statement of China RoHS Compliance 2 48 Chapter 3 Board Components Reference Additional Information Document Revision History Info 1 How to Contact Altera Info 1 Typographic Conventions Info 1 ...

Page 5: ...ed mezzanine card HSMC connectors are available to add additional functionality via a variety of HSMCs available from Altera and various partners f To see a list of the latest HSMCs available or to download a copy of the HSMC specification refer to the Development Board Daughtercards page of the Altera website Design advancements and innovations such as the PCI Express hard IP partial reconfigurat...

Page 6: ...MAX V CPLD 5M2210ZF256C4N in a 256 pin FBGA package as the System Controller Flash fast passive parallel FPP configuration MAX II CPLD EPM240M100C4N in a 100 pin FBGA package as part of the embedded USB BlasterTM II for use with the Quartus II Programmer Clocking circuitry Programmable clock generator for the FPGA reference clock input 125 MHz LVDS oscillator for the FPGA reference clock input 148...

Page 7: ...width LEDs Five Ethernet LEDs One serial digital interface SDI carrier detect LED One power on LED One two line character LCD display Push buttons One CPU reset push button One MAX V reset push button One program select push button One program configuration push button Three general user push buttons DIP switches Board settings DIP switch JTAG chain control DIP switch PCI Express link width DIP sw...

Page 8: ...ndling the board can be damaged Therefore use anti static handling precautions when touching the board Figure 1 1 Cyclone V GX FPGA Development Board Block Diagram LVDS Single Ended 128 MB DDR3 128 MB DDR3 2x16 LCD Push Buttons DIP Switches LEDs 18 MB SSRAM 512 MB Flash x4 Edge Trigger SMA Out REFCLK SMA In Gigabit Ethernet PHY Embedded USB Blaster II Type B USB 2 0 XCVR x1 SDI TX RX XCVR x1 Debug...

Page 9: ...t board reside in the Cyclone V GX FPGA development kit documents directory f For information about powering up the board and installing the demonstration software refer to the Cyclone V GX FPGA Development Kit User Guide This chapter consists of the following sections Board Overview Featured Device Cyclone V GX FPGA on page 2 5 MAX V CPLD 5M2210 System Controller on page 2 6 FPGA Configuration on...

Page 10: ...ut SMA Connector J4 HSMC Port J1 Configuration Done Load and Error LEDs D15 D17 Program Config Program Select Push Buttons S6 S7 Program Select LEDs D12 D14 Transceiver SMA Connectors RX J2 J6 TX J3 J7 USB Type B Connector J12 SDI Video Port J5 J10 Debug Header J14 Gigabit Ethernet Port J11 JTAG Chain Header J13 Fan Power Header J8 PCI Express Mode DIP Switch SW4 JTAG Chain Control DIP Switch SW5 ...

Page 11: ...HSMC port LEDs You can configure these LEDs to indicate transmit or receive activity D3 HSMC port present LED Illuminates when a daughtercard is plugged into the HSMC port A D8 D9 D10 PCI Express link LEDs You can configure these LEDs to indicate the PCI Express link width x1 x4 and Gen1 link Clock Circuitry U25 Quad output oscillator Programmable oscillator with default frequencies of 125 MHz 409...

Page 12: ...nnels and 84 CMOS or 17 LVDS channels per the HSMC specification J11 Gigabit Ethernet port RJ 45 connector which provides a 10 100 1000 Ethernet connection via a Marvell 88E1111 PHY and the FPGA based Altera Triple Speed Ethernet MegaCore function in RGMII mode Video and Display Ports J18 Character LCD Connector that interfaces to a provided 16 character 2 line LCD module along with two standoffs ...

Page 13: ...ble 2 2 Cyclone V GX FPGA Features ALMs Equivalent LEs M10K RAM Blocks Total RAM Kbits 18 bit 18 bit Multipliers PLLs Transceivers Package Type 136 880 150 000 1 726 7 024 312 7 9 896 pin FBGA Table 2 3 Cyclone V GX Device I O Pin Count Function I O Standard I O Count Special Pins DDR3A 1 5 V SSTL 81 One differential x4 DQS pin DDR3B 1 5 V SSTL 81 One differential x4 DQS pin Flash SSRAM and MAX V ...

Page 14: ...Blaster II Si571 Controller Si5538 Controller SLD HUB PFL FSM Bus MAX V CPLD System Controller Power Measurement Results Virtual JTAG PC FPGA LTC2418 Controller Flash Decoder Encoder GPIO JTAG Control SSRAM Control Register Si571 Programmable Oscillator Si5338 Programmable Oscillator Table 2 4 MAX V CPLD 5M2210 System Controller Device Pin Out Part 1 of 5 Board Reference U12 Schematic Signal Name ...

Page 15: ...ration data H15 FPGA_CONFIG_D2 2 5 V FPGA configuration data C15 FPGA_CONFIG_D3 2 5 V FPGA configuration data E16 FPGA_CONFIG_D4 2 5 V FPGA configuration data D16 FPGA_CONFIG_D5 2 5 V FPGA configuration data F14 FPGA_CONFIG_D6 2 5 V FPGA configuration data E15 FPGA_CONFIG_D7 2 5 V FPGA configuration data G13 FPGA_CONFIG_D8 2 5 V FPGA configuration data H14 FPGA_CONFIG_D9 2 5 V FPGA configuration d...

Page 16: ...ess bus J3 FSM_A16 2 5 V FSM address bus G1 FSM_A17 2 5 V FSM address bus F3 FSM_A18 2 5 V FSM address bus D3 FSM_A19 2 5 V FSM address bus C3 FSM_A20 2 5 V FSM address bus G4 FSM_A21 2 5 V FSM address bus F4 FSM_A22 2 5 V FSM address bus E3 FSM_A23 2 5 V FSM address bus C2 FSM_A24 2 5 V FSM address bus H2 FSM_A25 2 5 V FSM address bus H3 FSM_A26 2 5 V FSM address bus R3 FSM_D0 2 5 V FSM data bus ...

Page 17: ...N 2 5 V FSM bus MAX V output enable A10 MAX5_WEN 2 5 V FSM bus MAX V write enable L13 MAX_CONF_DONEN 2 5 V Embedded USB Blaster II configuration done LED P14 MAX_ERROR 2 5 V FPGA configuration error LED D14 MAX_LOAD 2 5 V FPGA configuration active LED M9 MAX_RESETN 2 5 V MAX V reset push button F11 MSEL0 2 5 V FPGA mode select 0 F12 MSEL1 2 5 V FPGA mode select 1 K12 MSEL2 2 5 V FPGA mode select 2...

Page 18: ... V Power monitor SPI clock G12 SENSE_SDI 2 5 V Power monitor SPI data in C14 SENSE_SDO 2 5 V Power monitor SPI data out J1 SI571_EN 2 5 V Si571 programmable VCXO enable R8 USB_CFG0 2 5 V Embedded USB Blaster II interface Reserved for future use T7 USB_CFG1 2 5 V Embedded USB Blaster II interface Reserved for future use R4 USB_CFG2 2 5 V Embedded USB Blaster II interface Reserved for future use R9 ...

Page 19: ...rol DIP switch SW5 controls the jumpers shown in Figure 2 3 To connect a device or interface in the chain their corresponding switch must be in the OFF position Slide all the switches in the ON position to only have the FPGA in the chain 1 The MAX V CPLD 5M2210 System Controller must be in the JTAG chain to use some of the GUI interfaces Figure 2 3 JTAG Chain Embedded USB Blaster II GPIO TCK Cyclo...

Page 20: ...3 3 V USB 2 0 PHY port A interface C7 FX2_PA6 3 3 V USB 2 0 PHY port A interface C6 FX2_PA7 3 3 V USB 2 0 PHY port A interface H3 FX2_PB0 3 3 V USB 2 0 PHY port B interface F4 FX2_PB1 3 3 V USB 2 0 PHY port B interface H4 FX2_PB2 3 3 V USB 2 0 PHY port B interface G4 FX2_PB3 3 3 V USB 2 0 PHY port B interface H5 FX2_PB4 3 3 V USB 2 0 PHY port B interface G5 FX2_PB5 3 3 V USB 2 0 PHY port B interfa...

Page 21: ...his method is used to restore the development board to its factory default settings Other methods to program the flash memory can be used as well including the Nios II processor f For more information on the Nios II processor refer to the Nios II Processor page of the Altera website On either power up or by pressing the program configuration push button PGM_CONFIG S6 the MAX V CPLD 5M2210 System C...

Page 22: ...TAG masters the embedded USB Blaster is automatically disabled when you connect an external USB Blaster to the JTAG chain through the JTAG chain header Figure 2 4 PFL Configuration MAX V CPLD 5M2210 System Controller Cyclone V FPGA FPGA_DATA 15 0 FPGA_DCLK FLASH_A 25 1 FLASH_D 31 0 DATA 15 0 DCLK nSTATUS nCONFIG CONF_DONE CONF_DONE MSEL 4 0 Connects to the MAX V CPLD 2 5 V 10 kΩ nCE CFI Flash FLAS...

Page 23: ...s Illuminates to indicate which hardware page loads from flash memory when you press the PGM_SEL push button D27 D26 D28 D25 JTAG_RX JTAG_TX SC_RX SC_TX 2 5 V Green LEDs Illuminates to indicate USB Blaster II receive and transmit activities D19 ENET_LED_TX 2 5 V Green LED Illuminates to indicate Ethernet PHY transmit activity Driven by the Marvell 88E1111 PHY D22 ENET_LED_RX 2 5 V Green LED Illumi...

Page 24: ...either remove or include devices in the active JTAG chain The Cyclone V GX FPGA is always in the JTAG chain Table 2 9 lists the switch controls and its descriptions Table 2 8 Board Settings DIP Switch Controls Switch Schematic Signal Name Description Default 1 CLK_SEL ON Select SMA input clock OFF Select programmable oscillator clock OFF 2 CLK_EN ON Disable on board oscillator OFF Enable on board ...

Page 25: ... Controller This input forces a FPGA reconfiguration from the flash memory The location in the flash memory is based on the settings of PGM_LED 2 0 which is controlled by the program select push button PGM_SEL Valid settings include PGM_LED0 PGM_LED1 or PGM_LED2 on the three pages in flash memory reserved for FPGA designs Program Select Push Button The program select push button PGM_SEL S7 is an i...

Page 26: ...GA Development Board Clocks SMA SMA HSMC XVCR x4 SDI x1 CH0 125 MHz CH2 156 25 MHz Si5338 x4 LVDS Output CH1 IN1 IN1 IN2 CH2 CH3 CH1 CH0 CH2 CH3 SL18860DC Clock Fan Out x3 SE To Bank 4A USB Clock 48 MHz IDT5T9306 Clock Fan Out x4 LVDS Si510 SE 50 MHz Fixed Oscillator Si510 SE 50 MHz Fixed Oscillator 25 MHz Fixed Oscillator MAX V CPLD System Controller Cyclone V GX FPGA FA 128 24 0 MB W 24 MHz XTAL...

Page 27: ...W8 PCI Express x4 PCIE_REFCLK_N W7 U25 CLKIN_BANK3B_125_R_P 125 000 MHz 1 5V LVDS fanout buffer Y15 Bottom edge CLKIN_BANK3B_125_R_N AA15 CLKIN_BANK4A_125_R_P AC15 CLKIN_BANK4A_125_R_N AB16 REFCLK1_Q2L_P P8 HSMC port A REFCLK1_Q2L_N N7 X2 CLK_148_P 148 500 MHz LVDS R8 HD SDI video CLK_148_N R7 Table 2 12 Off Board Clock Inputs Source Schematic Signal Name I O Standard Cyclone V GX Pin Number Descr...

Page 28: ...nal names and their corresponding Cyclone V GX device pin numbers User Defined DIP Switch Board reference SW2 is a four pin DIP switch This switch is user defined and provides additional FPGA input control When the switch is in the OFF position a logic 1 is selected When the switch is in the ON position a logic 0 is selected There are no board specific functions for this switch Table 2 13 Off Boar...

Page 29: ...1 and D2 are LEDs for the HSMC port There are no board specific functions for the HSMC LEDs The LEDs are labeled TX and RX and are intended to display data flow to and from the connected daughtercards The LEDs are driven by the Cyclone V GX device Table 2 17 lists the HSMC LED schematic signal names and their corresponding Cyclone V GX device pin numbers Table 2 15 User Defined DIP Switch Schemati...

Page 30: ...mmarizes the character LCD pin assignments The signal names and directions are relative to the Cyclone V GX device Table 2 18 PCI Express LED Schematic Signal Names and Functions Board Reference Schematic Signal Name Cyclone V GX Pin Number I O Standard Description D8 PCIE_LED_X1 AD28 2 5 V Green LED Configure this LED to display the PCI Express link width x1 D9 PCIE_LED_X4 AC29 2 5 V Green LED Co...

Page 31: ...20 LCD Pin Definitions and Functions Pin Number Symbol Level Function 1 VDD Power supply 5 V 2 VSS GND 0 V 3 V0 For LCD drive 4 RS H L Register select signal H Data input L Instruction input 5 R W H L H Data read module to MPU L Data write MPU to module 6 E H H to L Enable 7 14 DB0 DB7 H L Data bus software selectable 4 bit or 8 bit mode Table 2 21 Debug Header Pin Assignments Schematic Signal Nam...

Page 32: ...ting channel width from 1 to 4 by using Altera s PCIe MegaCore IP You can also configure this board to a 1 or 4 interface through a DIP switch that connects the PRSNTn pins for each bus width The PCI Express interface has a connection speed of 2 5 Gbps lane for a maximum of 20 Gbps full duplex Gen1 The power for the board can be sourced entirely from the PCI Express edge connector when installed i...

Page 33: ...G chain clock A6 PCIE_JTAG_TDI LVTTL JTAG chain data in A7 PCIE_JTAG_TDO LVTTL JTAG chain data out A8 PCIE_JTAG_TMS LVTTL JTAG chain mode select A11 PCIE_PERSTN W27 LVTTL Reset A1 PCIE_PRSNT1N LVTTL Link width DIP switch B17 PCIE_PRSNT2N_X1 LVTTL Hot plug present detect B31 PCIE_PRSNT2N_X4 LVTTL Hot plug present detect A13 PCIE_REFCLK_P W8 HCSL Reference clock input A14 PCIE_REFCLK_N W7 HCSL Refer...

Page 34: ...3 Y3 1 5 V PCML Transmit bus B11 PCIE_WAKEn Y27 2 5 V Wake signal Table 2 22 PCI Express Pin Assignments Schematic Signal Names and Functions Board Reference J19 Schematic Signal Name Cyclone V GX Pin Number I O Standard Description Figure 2 7 RGMII Interface between FPGA MAC and Marvell 88E1111 PHY 10 100 1000 Mbps Ethernet MAC Marvell 88E1111 PHY Device Transformer RJ45 RGMII Interface TXD 3 0 R...

Page 35: ... 5 V CMOS RGMII receive clock 95 ENET_RX_D0 AF8 2 5 V CMOS RGMII receive data bus 92 ENET_RX_D1 AB9 2 5 V CMOS RGMII receive data bus 93 ENET_RX_D2 AA9 2 5 V CMOS RGMII receive data bus 91 ENET_RX_D3 AH7 2 5 V CMOS RGMII receive data bus 94 ENET_RX_DV D19 2 5 V CMOS RGMII receive data valid 11 ENET_TX_D0 AG7 2 5 V CMOS RGMII transmit data bus 12 ENET_TX_D1 AB8 2 5 V CMOS RGMII transmit data bus 14...

Page 36: ...ut not limited to LVDS mini LVDS and RSDS with up to 17 full duplex channels 1 As noted in the High Speed Mezzanine Card HSMC Specification manual LVDS and single ended I O standards are only guaranteed to function when mixed according to either the generic single ended pin out or generic differential pin out Table 2 24 lists the HSMC interface pin assignments signal names and functions Figure 2 8...

Page 37: ...D12 LVDS or 2 5 V LVDS TX bit 0 or CMOS bit 4 48 HSMA_RX_D_P0 E11 LVDS or 2 5 V LVDS RX bit 0 or CMOS bit 5 49 HSMA_TX_D_N0 C12 LVDS or 2 5 V LVDS TX bit 0n or CMOS bit 6 50 HSMA_RX_D_N0 D10 LVDS or 2 5 V LVDS RX bit 0n or CMOS bit 7 53 HSMA_TX_D_P1 D14 LVDS or 2 5 V LVDS TX bit 1 or CMOS bit 8 54 HSMA_RX_D_P1 H12 LVDS or 2 5 V LVDS RX bit 1 or CMOS bit 9 55 HSMA_TX_D_N1 C14 LVDS or 2 5 V LVDS TX ...

Page 38: ...P8 F19 LVDS or 2 5 V LVDS RX bit 8 or CMOS bit 41 103 HSMA_TX_D_N8 B21 LVDS or 2 5 V LVDS TX bit 8n or CMOS bit 42 104 HSMA_RX_D_N8 E18 LVDS or 2 5 V LVDS RX bit 8n or CMOS bit 43 107 HSMA_TX_D_P9 A21 LVDS or 2 5 V LVDS TX bit 9 or CMOS bit 44 108 HSMA_RX_D_P9 D20 LVDS or 2 5 V LVDS RX bit 9 or CMOS bit 45 109 HSMA_TX_D_N9 A20 LVDS or 2 5 V LVDS TX bit 9n or CMOS bit 46 110 HSMA_RX_D_N9 C19 LVDS o...

Page 39: ...t 14 or CMOS bit 65 139 HSMA_TX_D_N14 C26 LVDS or 2 5 V LVDS TX bit 14n or CMOS bit 66 140 HSMA_RX_D_N14 G23 LVDS or 2 5 V LVDS RX bit 14n or CMOS bit 67 143 HSMA_TX_D_P15 B27 LVDS or 2 5 V LVDS TX bit 15 or CMOS bit 68 144 HSMA_RX_D_P15 H21 LVDS or 2 5 V LVDS RX bit 15 or CMOS bit 69 145 HSMA_TX_D_N15 A28 LVDS or 2 5 V LVDS TX bit 15n or CMOS bit 70 146 HSMA_RX_D_N15 G21 LVDS or 2 5 V LVDS RX bit...

Page 40: ...d Table 2 26 SDI Video Output Interface Pin Assignments Schematic Signal Names and Functions Board Reference U1 Schematic Signal Name Cyclone V GX Pin Number I O Standard Description 1 SDI_TX_P V4 1 5 V PCML Serial data input P 2 SDI_TX_N V3 1 5 V PCML Serial data input N 4 SDI_TX_RSET 2 5 V Output swing set resistor 6 SDI_TX_EN AJ1 2 5 V Output driver enable 7 SDI_SDA R20 2 5 V Cable driver I2C b...

Page 41: ...x8 DDR3 SDRAM interfaces for very high speed sequential memory access The DDR3 SDRAM has two independent interfaces DDR3A x32 interface using a hard memory controller vertical I O banks on the bottom edge of the FPGA DDR3B x32 interface using a soft memory controller horizontal I O banks on the right edge of the FPGA Each 32 bit data bus comprises of two x16 devices and one x8 device for ECC suppo...

Page 42: ... Class I Address bus N7 DDR3A_A12 AJ7 1 5 V SSTL Class I Address bus T3 DDR3A_A13 AK7 1 5 V SSTL Class I Address bus M2 DDR3A_BA0 AH9 1 5 V SSTL Class I Bank address bus N8 DDR3A_BA1 AH10 1 5 V SSTL Class I Bank address bus M3 DDR3A_BA2 AJ10 1 5 V SSTL Class I Bank address bus K3 DDR3A_CASN AF9 1 5 V SSTL Class I Row address select K9 DDR3A_CKE AK18 1 5 V SSTL Class I Column address select J7 DDR3...

Page 43: ...Class I Reset L3 DDR3A_WEN AK5 1 5 V SSTL Class I Write enable L8 DDR3A_ZQ01 1 5 V SSTL Class I ZQ impedance calibration DDR3 x16 U22 N3 DDR3A_A0 AJ12 1 5 V SSTL Class I Address bus P7 DDR3A_A1 AK12 1 5 V SSTL Class I Address bus P3 DDR3A_A2 AH11 1 5 V SSTL Class I Address bus N2 DDR3A_A3 AH12 1 5 V SSTL Class I Address bus P8 DDR3A_A4 AG13 1 5 V SSTL Class I Address bus P2 DDR3A_A5 AG14 1 5 V SST...

Page 44: ...DR3A_DQ26 AH24 1 5 V SSTL Class I Data bus byte lane 3 A7 DDR3A_DQ27 AK25 1 5 V SSTL Class I Data bus byte lane 3 A3 DDR3A_DQ28 AE20 1 5 V SSTL Class I Data bus byte lane 3 C3 DDR3A_DQ29 AD19 1 5 V SSTL Class I Data bus byte lane 3 B8 DDR3A_DQ30 AG24 1 5 V SSTL Class I Data bus byte lane 3 C8 DDR3A_DQ31 AK26 1 5 V SSTL Class I Data bus byte lane 3 F3 DDR3A_DQS_P2 Y20 Differential 1 5 V SSTL Class ...

Page 45: ...L Class I Differential output clock H2 DDR3A_CSN Y12 1 5 V SSTL Class I Chip select B7 DDR3A_DM4 AG23 1 5 V SSTL Class I Write mask byte lane E3 DDR3A_DQ32 AG21 1 5 V SSTL Class I Data bus byte lane 4 C8 DDR3A_DQ33 AF20 1 5 V SSTL Class I Data bus byte lane 4 E7 DDR3A_DQ34 AK27 1 5 V SSTL Class I Data bus byte lane 4 B3 DDR3A_DQ35 AH26 1 5 V SSTL Class I Data bus byte lane 4 D2 DDR3A_DQ36 AG22 1 5...

Page 46: ...SSTL Class I Address bus N7 DDR3B_A12 T25 1 5 V SSTL Class I Address bus T3 DDR3B_A13 AD29 1 5 V SSTL Class I Address bus M2 DDR3B_BA0 W30 1 5 V SSTL Class I Bank address bus N8 DDR3B_BA1 T24 1 5 V SSTL Class I Bank address bus M3 DDR3B_BA2 V30 1 5 V SSTL Class I Bank address bus K3 DDR3B_CASN T30 1 5 V SSTL Class I Row address select K9 DDR3B_CKE L28 1 5 V SSTL Class I Column address select J7 DD...

Page 47: ...lass I Reset L3 DDR3B_WEN T28 1 5 V SSTL Class I Write enable L8 DDR3B_ZQ01 1 5 V SSTL Class I ZQ impedance calibration DDR3 x16 U15 N3 DDR3B_A0 Y30 1 5 V SSTL Class I Address bus P7 DDR3B_A1 R28 1 5 V SSTL Class I Address bus P3 DDR3B_A2 AA29 1 5 V SSTL Class I Address bus N2 DDR3B_A3 W29 1 5 V SSTL Class I Address bus P8 DDR3B_A4 U23 1 5 V SSTL Class I Address bus P2 DDR3B_A5 AA30 1 5 V SSTL Cla...

Page 48: ...R3B_DQ26 G27 1 5 V SSTL Class I Data bus byte lane 3 C2 DDR3B_DQ27 L25 1 5 V SSTL Class I Data bus byte lane 3 A7 DDR3B_DQ28 L29 1 5 V SSTL Class I Data bus byte lane 3 A2 DDR3B_DQ29 N27 1 5 V SSTL Class I Data bus byte lane 3 B8 DDR3B_DQ30 K26 1 5 V SSTL Class I Data bus byte lane 3 A3 DDR3B_DQ31 L26 1 5 V SSTL Class I Data bus byte lane 3 F3 DDR3B_DQS_P2 N22 Differential 1 5 V SSTL Class I Data ...

Page 49: ...STL Class I Differential output clock H2 DDR3B_CSN U29 1 5 V SSTL Class I Chip select B7 DDR3B_DM4 P29 1 5 V SSTL Class I Write mask byte lane B3 DDR3B_DQ32 P28 1 5 V SSTL Class I Data bus byte lane 4 C7 DDR3B_DQ33 K28 1 5 V SSTL Class I Data bus byte lane 4 C2 DDR3B_DQ34 M27 1 5 V SSTL Class I Data bus byte lane 4 C8 DDR3B_DQ35 P30 1 5 V SSTL Class I Data bus byte lane 4 E3 DDR3B_DQ36 N29 1 5 V S...

Page 50: ...unctions Part 1 of 2 Board Reference U37 Schematic Signal Name Cyclone V GX Pin Number I O Standard Description 86 FLASH_OEN M8 2 5 V Output enable 87 FLASH_WEN J15 2 5 V Write enable 37 FSM_A1 N10 2 5 V Address bus 36 FSM_A2 N9 2 5 V Address bus 44 FSM_A3 M12 2 5 V Address bus 42 FSM_A4 M11 2 5 V Address bus 34 FSM_A5 G7 2 5 V Address bus 47 FSM_A6 G8 2 5 V Address bus 43 FSM_A7 F6 2 5 V Address ...

Page 51: ...M_D8 B8 2 5 V Data bus 22 FSM_D9 C9 2 5 V Data bus 19 FSM_D10 A9 2 5 V Data bus 18 FSM_D11 A10 2 5 V Data bus 12 FSM_D12 C10 2 5 V Data bus 13 FSM_D13 D9 2 5 V Data bus 8 FSM_D14 A11 2 5 V Data bus 9 FSM_D15 B11 2 5 V Data bus 85 SRAM_ADSCN P12 2 5 V Address status controller 84 SRAM_ADSPN J13 2 5 V Address status processor 83 SRAM_ADVN K13 2 5 V Adress valid 93 SRAM_BWAN P10 2 5 V Byte write sele...

Page 52: ...ess bus C4 FSM_A12 E7 2 5 V Address bus A5 FSM_A13 D6 2 5 V Address bus B5 FSM_A14 D7 2 5 V Address bus C5 FSM_A15 A2 2 5 V Address bus D7 FSM_A16 A3 2 5 V Address bus D8 FSM_A17 D8 2 5 V Address bus A7 FSM_A18 E8 2 5 V Address bus B7 FSM_A19 F8 2 5 V Address bus C7 FSM_A20 G9 2 5 V Address bus C8 FSM_A21 H9 2 5 V Address bus A8 FSM_A22 J9 2 5 V Address bus G1 FSM_A23 H7 2 5 V Address bus H8 FSM_A...

Page 53: ...igital converter ADC measures the current for several specific board rails H7 FSM_D7 B7 2 5 V Data bus E1 FSM_D8 B8 2 5 V Data bus E3 FSM_D9 C9 2 5 V Data bus F3 FSM_D10 A9 2 5 V Data bus F4 FSM_D11 A10 2 5 V Data bus F5 FSM_D12 C10 2 5 V Data bus H5 FSM_D13 D9 2 5 V Data bus G7 FSM_D14 A11 2 5 V Data bus E7 FSM_D15 B11 2 5 V Data bus Table 2 32 Flash Pin Assignments Schematic Signal Names and Fun...

Page 54: ... 5 V Switcher 6 0 A 5 LTC3855 Channel 1 1 1 V Switcher 6 0 A 30 mV LTC3025 1 1 8 V LDO 115 mA 5 LTC3025 1 1 0 V LDO 304 mA 5 LTC3009 5 0 V LDO 9 12 mA 5 LTC3009 5 37 V LDO 20 mA 5 14 V 20 V DC INPUT 12 V 3 V 3 3 V 2 8 A 12 V 3 2 A 2 5 V 2 4 A 2 5 V 3 5 A 1 5 V 6 0 A 1 1 V 6 0 A 5 37 V 0 3 mA 5 0 V 9 12 mA 12 V 3 3 V 3 3 V 12 V Filter Ethernet PHY SSRAM Flash MAX V VCCIO MAX II VCCIO MAX II VCCint ...

Page 55: ...ed to the rail Figure 2 11 Power Measurement Circuit SCK SPI Bus DSI DSO CSn 8 Ch Power Supply Load 0 7 RSENSE MAX V CPLD 5M2210 System Controller Cyclone V GX FPGA To User PC JTAG Chain Feedback 14 pin 2x16 Character LCD E RW RS D 0 7 Supply 0 7 EPM570 USB PHY Embedded USB Blaster II Table 2 34 Power Measurement Rails Channel Schematic Signal Name Voltage V Device Pin Description 1 C5_VCC_VCCE_GX...

Page 56: ...ominated biphenyls PBB Polybrominated diphenyl Ethers PBDE Cyclone V GX development board X 0 0 0 0 0 15 V power supply 0 0 0 0 0 0 Type A B USB cable 0 0 0 0 0 0 User guide 0 0 0 0 0 0 Notes to Table 2 35 1 0 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the SJ T11363 2006 standard 2 X indicates that the co...

Page 57: ...sition DIP switch C K Components ITT Industries TDA04H0SB1 www ittcannon com S1 S4 S6 S7 Push button Panasonic EVQPAC07K www panasonic com S3 S5 Push button Dawning Precision Co TS A02SA 2 S100 www dawning2 com tw U25 Programmable LVDS quad clock 125M 409 6M 156 25M 100M defaults Silicon Labs Si5338A A01343 GM www silabs com X2 148 50 MHz LVDS voltage controlled crystal oscillator Silicon Labs 571...

Page 58: ...RAM Micron MT41J128M16 www micron com U19 U23 16M 8 8 128 MB DDR3 SDRAM Micron MT41J128M8 www micron com U37 1024K 18 bit 18 MB synchronous SRAM Integrated Silicon Solution Inc IS61VPS102418A 250TQL www issi com U18 512 MB synchronous flash Numonyx PC28F512P30BF www numonyx com U17 16 channel differential 24 bit ADC Linear Technology LTC2418CGN PBF www linear com Table 3 1 Component Reference and ...

Page 59: ...d the power inputs in Table 2 33 Updated Figure 2 4 September 2012 1 0 Initial release Contact 1 Contact Method Address Technical support Website www altera com support Technical training Website www altera com training Email custrain altera com Product literature Website www altera com literature Nontechnical support general Email nacomp altera com software licensing Email authorization altera co...

Page 60: ... references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI r An angled arrow instructs you to press the Enter key 1 2 3 and a b c and so on Numbered steps indicate a list of items when the sequence of the items is important such as the steps listed in a procedure Bullets indicate a list of items when the sequence of the items is not important 1 Th...

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