ADM-XRC-7Z2 User Manual
V1.2 - 24th Feb 2020
Signal
Target FPGA Input
IO Standard
"P" pin
"N" pin
BU_REFCLK40M
IO_L13_MRCC_12
LVCMOS33
AE28
-
Table 14 : BU_REFCLK40M Connections
4.5.10 BU_HOST_CLK
In addition to the reference clocks, there is an additional clock, BU_HOST_CLK, used for the local bus interface
between the Zynq PL and the BU-67301. Two phase-matched copies of BU_HOST_CLCK_OUT should be
generated by the Zynq PL on pins AD25 and AE26.
BU_HOST_CLK_OUT_A on pin AD25 is connected to the HOST_CLK input on the BU-67301.
BU_HOST_CLK_OUT_B on pin AE26 is connected back in to the PL on pin AC28 as "BU_HOST_CLK".
4.6 Resets
The Zynq PS can be reset using the System Reset switch, SW2-8.
Page 12
Functional Description
ad-ug-1273_v1_2.pdf
