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ADM-XRC-7Z1 User Manual

V2.6 - 14th February 2022

Appendix B: Front (XRM) Connector Pinouts

The XRM interface consists of two connectors: CN1 and CN2. CN1 is a 180-way Samtec QSH in 3 fields. It is for

general-purpose signals, power and module control. CN2 is a 28-way Samtec QSE-DP for high-speed serial

(MGT) links.

Power

JTAG & Platform Management

General Purpose I/O

Clocks

MGT Links

Page 24

Front (XRM) Connector Pinouts

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Summary of Contents for ADM-XRC-7Z1

Page 1: ...ADM XRC 7Z1 User Manual Document Revision 2 6 14th February 2022...

Page 2: ...form without prior written consent from Alpha Data Parallel Systems Ltd Head Office Address Suite L4A 160 Dundee Street Edinburgh EH11 1DQ UK Telephone 44 131 558 2600 Fax 44 131 558 2700 email sales...

Page 3: ...4 2 1 XMC Platform Interface 8 4 2 1 1 IPMI I2C 8 4 2 1 2 MBIST 8 4 2 1 3 MVMRO 8 4 2 1 4 MRSTI 8 4 2 1 5 MRSTO 8 4 2 1 6 MPRESENT 9 4 2 1 7 JTAG 9 4 2 2 P5 HSSIO Links 9 4 3 Secondary XMC Connector P...

Page 4: ...RM Connector Pinouts 24 B 1 XRM Connector CN1 Field 1 25 B 2 XRM Connector CN1 Field 2 26 B 3 XRM Connector CN1 Field 3 27 B 4 XRM Connector CN2 28 Appendix C XMC Breakout FPGA Pinout 29 List of Table...

Page 5: ...22 Table 26 PMC Connector P4 23 Table 27 XRM Connector CN1 Field 1 25 Table 28 XRM Connector CN1 Field 2 26 Table 29 XRM Connector CN1 Field 3 27 Table 30 XRM Connector CN2 28 Table 31 XMC Connector...

Page 6: ...ADM XRC 7Z1 User Manual V2 6 14th February 2022 Page Intentionally left blank...

Page 7: ...ort to micro USB connector Commercial Spec Option Programmable Logic PL Block consisting of 2 banks of DDR3 SDRAM 256MB per bank Ethernet interface to rear panel P4 connector Serial COM port connectio...

Page 8: ...ase check with Alpha Data sales for details 1 4 References Specifications ANSI VITA 42 0 XMC Standard December 2008 VITA ISBN 1 885731 49 3 ANSI VITA 42 3 XMC PCI Express Protocol Layer Standard June...

Page 9: ...or P6 on the card is not compatible with the VITA 42 10 XMC GPIO Standard In particular USB VCC must not be applied on this connector The PMC connector P4 has the main interfaces to the ARM Processing...

Page 10: ...by electrostatic discharge ESD To prevent damage observe ESD precautions Always wear a wrist strap when handling the card Hold the board by the edges Avoid touching any components Store in ESD safe ba...

Page 11: ...Programmable Logic PL Sw microUSB 8 11 15 12 Platform Manager COM0 IPMI EPROM V T Sensors Ref Clocks Power Supplies 7 0 GTX Transceivers VPWR 5V or 12V I2 C 3 3V PCIE RefClk PCIE HSSIO 7 0 P5 P6 P6 Re...

Page 12: ...routed to P6 MGT 3 0 routed to XRM SW1 7 MGT 7 4 Mux Sel MGT 7 4 routed to P6 MGT 7 4 routed to XRM SW1 8 Reserved Table 4 Switch 1 Definitions Switch 1 Ref Function OFF State ON State SW2 1 BootSel...

Page 13: ...Green System Monitor Status See Table 23 D6 Red System Monitor Status See Table 23 D8 Green FPGA PL Done PL is configured PL is not configured D9 Green Flash Boot Enable Enable PS booting PL from fla...

Page 14: ...when the board is powered 4 2 1 3 MVMRO XMC Write Prohibit This signal is an input from the carrier When asserted high all writes to non volatile memories are inhibited Amber LED D10 indicates a warn...

Page 15: ...eight lanes are directly connected from the PL to the connector The Rx side of all eight lanes are AC coupled by 100nF capacitors placed at the input to the PL Alternative coupling options are availa...

Page 16: ...is protected by a poly fuse rated at 350mA 3 3V signals must not be used at header J3 or J4 The JTAG signals at the XMC interface use 3 3V signals and are connected through level translators to the o...

Page 17: ...0MHz reference clock MGTCLK250M is a differential clock signal using LVDS Two phase matched copies are MGTREFCLK inputs on the Zynq PL at GTX Quad 109 and 111 Since each input can clock the adjacent G...

Page 18: ...lock at the PS_CLK input on pin A22 This clock is asynchronous to the clocks generated by the Si5338B Signal Target FPGA Input IO Standard P pin N pin PS_CLK33M3 PS_CLK_500 LVCMOS18 A22 Table 13 PS_CL...

Page 19: ...2 3 PS DDR3 Memory The PS has one bank of DDR3 memory consisting of 2 16 bit wide memory devices in parallel to provide a 32 bit data path capable of running up to 533MHz DDR 1066 2Gb devices Micron...

Page 20: ...ADM XRC 7Z1 User Manual V2 6 14th February 2022 LED Colour Function 0 Green 1 Green 2 Amber Table 16 Ethernet Status LEDs Page 14 Functional Description ad ug 1253_v2_6 pdf...

Page 21: ...his case interface USB0 to the Zynq PS becomes a downstream port PS PHY ULPI 4 port Hub P4 USB1 USB2 Micro USB 0 0 0 ExtHostSel Figure 5 USB Interfaces 4 9 Zynq PL Block 4 9 1 PL DDR3 Memory The PL ha...

Page 22: ...e a common voltage XRM_VIO that can be either 1 8V 1 5V or 1 2V The required voltage is stored within the platform management PROM on the XRM Group FPGA Bank Name Function Group A 16 17 XRM_DA 15 0 16...

Page 23: ...ngs are as follows Signal FPGA Pin FPGA Pin Rear Connector Pin Rear Connector Pin P5_TX_0 N4 N3 P5 A1 P5 B1 P5_TX_1 P2 P1 P5 D1 P5 E1 P5_TX_2 R4 R3 P5 A3 P5 B3 P5_TX_3 T1 T1 P5 D3 P5 E3 P5_TX_4 V2 V1...

Page 24: ...gnal FPGA Pin FPGA Pin Rear Connector Pin Rear Connector Pin P6_X38s_0 AJ16 AK15 P5 C19 P5 C18 P5_X38s_1 AH18 AJ18 P5 F19 P5 F18 P5_X38s_2 AJ15 AK15 P5 C17 P5 C16 P5_X38s_3 AH17 AH16 P5 F17 P5 F16 P5_...

Page 25: ...rnal 3 3V Supply Temp1 microcontroller internal temperature Temp2 TMP422 internal temperature Temp3 FPGA on die temperature measured in TMP422 Table 21 Voltage and Temperature Monitors in microcontrol...

Page 26: ...10 2 System Monitor Status LEDs LEDs D5 Green and D6 Red indicate the microcontroller status LEDs Status Flashing Green Flashing Red alternate Service Mode Red Missing application firmware or invalid...

Page 27: ...7 VPWR 3 8 GND GND XMC_TDI GND GND 12V 9 VPWR 5 10 GND GND XMC_TDO GND GND GA0 11 PER0p0 PER0n0 MBIST PER0p1 PER0n1 VPWR 3 12 GND GND GA1 GND GND MPRESENT 13 PER0p2 PER0n2 3 3V AUX 2 PER0p3 PER0n3 VPW...

Page 28: ...ND GPIO_11N 9 GPIO_10P GPIO_11P 10 GND GND GPIO_8N GND GND GPIO_9N 11 P6_RXp0 P6_RXn0 GPIO_8P P6_RXp1 P6_RXn1 GPIO_9P 12 GND GND GPIO_6N GND GND GPIO_7N 13 P6_RXp2 P6_RXn2 GPIO_6P P6_RXp3 P6_RXn3 GPIO...

Page 29: ...ND ETH1_DA 13 14 ETH1_DC ETH1_DA 15 16 ETH1_DC GND 17 18 GND ETH1_DB 19 20 ETH1_DD ETH1_DB 21 22 ETH1_DD GND 23 24 GND USB1_D 25 26 USB2_D USB1_D 27 28 USB2_D USB1_VCC 29 30 USB2_VCC 31 32 33 34 35 36...

Page 30: ...of two connectors CN1 and CN2 CN1 is a 180 way Samtec QSH in 3 fields It is for general purpose signals power and module control CN2 is a 28 way Samtec QSE DP for high speed serial MGT links Power JTA...

Page 31: ...8 R23 19 20 V26 DA_N9 DA_N10 N27 21 22 T25 DA_N11 DA_P10 N26 23 24 T24 DA_P11 DA_N12 P24 25 26 P30 DA_P13 DA_P12 P23 27 28 R30 DA_N13 DA_N14 P29 29 30 V27 DA_P15 DA_P14 N29 31 32 W28 DA_N15 DB_N0 T23...

Page 32: ...4 AB30 85 86 AF25 DB_N15 DB_P14 AB29 87 88 AE25 DB_P15 DB_CC_P16 AE28 89 90 AA25 SB_1 DB_CC_N16 AF28 91 92 W23 SC_0 SA_1 V21 93 94 AA22 SC_1 SB_0 Y25 95 96 AA23 SD_0 DC_CC_P16 AC28 97 98 AA30 DC_N1 DC...

Page 33: ...AJ29 143 144 AK27 DC_P13 DC_N14 AH27 145 146 AG24 DD_P1 DC_P14 AH26 147 148 AG25 DD_N1 DD_P0 AG22 149 150 AK26 DC_N15 DD_N0 AH22 151 152 AJ26 DC_P15 DD_P2 AH23 153 154 AG19 DD_N3 DD_N2 AH24 155 156 AF...

Page 34: ...C_N1 MGT_C2M_P4 AK10 9 10 AH10 MGT_M2C_P4 MGT_C2M_N4 AK9 11 12 AH9 MGT_M2C_N4 MGT_C2M_P5 AK6 13 14 AJ8 MGT_M2C_P5 MGT_C2M_N5 AK5 15 16 AJ7 MGT_M2C_N5 MGT_C2M_P2 AE4 17 18 AF6 MGT_M2C_P2 MGT_C2M_N2 AE3...

Page 35: ...IO2 P6 C18 AK16 GPIO GPIO3 P6 F19 AH18 GPIO GPIO4 P6 F18 AJ18 GPIO GPIO5 P6 C17 AJ15 GPIO GPIO6 P6 C16 AK15 GPIO GPIO7 P6 F17 AH17 GPIO GPIO8 P6 F16 AH16 GPIO GPIO9 P6 C15 AJ14 GPIO GPIO10 P6 C14 AJ13...

Page 36: ...s 8 and 9 07 04 14 2 1 Section 4 1 2 Added figure showing LED locations 10 04 14 2 2 Appendix B Added XRM pinout 11 04 14 2 3 Section 4 8 5 Correction to USB description 16 12 15 2 4 Table 22 Removed...

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