ADM-XRC-7Z1 User Manual
V2.6 - 14th February 2022
4.6.5 REFCLK200M
The fixed 200MHz reference clock, REFCLK200M, is a differential clock signal using LVDS. Three
phase-matched copies are distributed to Global Clock inputs on the Zynq PL.
This clock can be used to generate application-specific clock frequencies using the PLLs within the Zynq PL. It
is also suitable as the reference clock for the IO delay control block (IDELAYCTRL) and memory interfaces.
Signal
Target FPGA Input
IO Standard
"P" pin
"N" pin
REFCLK200M_A
IO_L13_MRCCC_10
LVDS_25
AG17
AG16
REFCLK200M_B
IO_L12_MRCC_33
SSTL15
G5
G4
REFCLK200M_C
IO_L13_MRCC_33
SSTL15
F5
E5
Table 12 : REFCLK200M Connections
4.6.6 PS_CLK33M3
The Zynq PS is provided with a 33.333MHz reference clock at the PS_CLK input on pin A22. This clock is
asynchronous to the clocks generated by the Si5338B.
Signal
Target FPGA Input
IO Standard
"P" pin
"N" pin
PS_CLK33M3
PS_CLK_500
LVCMOS18
A22
-
Table 13 : PS_CLK33M3 Connections
4.6.7 USB_REFCLK24M
The USB PHY and hub are provided with an independent 24.0MHz reference clock. This clock is asynchronous
to the clocks generated by the Si5338B and is not connected to the Zynq SoC.
4.6.8 ETH_CLK25M
The Ethernet PHYs are provided with 25.0MHz reference clocks generated by the Si5338B. These are not
connected to the Zynq SoC.
4.6.9 ETH1_CLK125M
The Ethernet PHY 1 generates a 125MHz reference clock that is connected to the Zynq PL at pin AF14.
Signal
Target FPGA Input
IO Standard
"P" pin
"N" pin
ETH1_CLK125M
IO_L12_MRCC_10
LVCMOS25
AF14
-
Table 14 : ETH1_CLK125M Connections
4.7 Resets
The Zynq PS can be reset using the System Reset switch, SW2-8.
Page 12
Functional Description
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