Alpha Data ADM-XRC-7Z1, User Manual

Page: 14 / 36

ADM-XRC-7Z1 User Manual
V2.6 - 14th February 2022
A further two sets of three LEDs provide an indication of the status of the two Ethernet interfaces
Comp. Ref. Function ON State Off State
D23 (Green)
Ethernet 0
LED0
See Table 16
D22 (Green)
Ethernet 0
LED1
See Table 16
D21 (Amber)
Ethernet 0
LED2
See Table 16
D20 (Green)
Ethernet 1
LED0
See Table 16
D19 (Green)
Ethernet 1
LED1
See Table 16
D17 (Amber)
Ethernet 1
LED2
See Table 16
Table 7 : Ethernet LED Definitions
4.2 Primary XMC Connector P5
Full pinout information for this connector is listed in Table 24
4.2.1 XMC Platform Interface
4.2.1.1 IPMI I2C
A 2 Kbit I2C EEPROM (type M24C02) is connected to the XMC IPMI. This memory contains board information
(type, voltage requirements etc.) as defined in the XMC based specification.
4.2.1.2 MBIST#
Built-In Self Test. This output signal is not used and is driven inactive (high) by the CPLD when the board is
powered.
4.2.1.3 MVMRO
XMC Write Prohibit. This signal is an input from the carrier. When asserted (high), all writes to non-volatile
memories are inhibited. Amber LED D10 indicates a warning when this signal is not set and writes to
non-volatile memory are enabled. The signal has a 100k pull-up resistor to assert it by default.
This signal cannot be internally driven or over-ridden. A buffered version of the signal is connected to the Zynq
PS at MIO50 (pin A19).
4.2.1.4 MRSTI#
XMC Reset In. This signal is an active low input from the carrier and should be used to reset any PCIE endpoint.
It is translated to 1.5V levels and connected to the Zynq PL at pin K2.
MRSTI# can also be used to fully reset the board by asserting the Zynq PS_POR_B input. This may not be
desirable and can be inhibited by turning switch SW2-5 ON.
4.2.1.5 MRSTO#
XMC Reset Out. This optional output signal is connected to the Zynq PL at pin J4. It should only be driven when
the board is connected to a master or Root Complex carrier slot.
Page 8 Functional Description
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