ADM-SDEV-BASE/XCKU060 User Manual
V1.0 - 27th November 2018
Table 10
Temperature Limits .......................................................................................................................... 14
Table 11
Status LED Definitions ..................................................................................................................... 14
Table 12
Target FPGA IO Banks .................................................................................................................... 15
Table 13
Target MGT Links ............................................................................................................................ 15
Table 14
LPC FMC Groups (J1) ..................................................................................................................... 18
Table 15
Config FMC Groups (J2) .................................................................................................................. 18
Table 16
FMC+ Groups (J3) ........................................................................................................................... 18
List of Figures
Figure 1
ADM-SDEV-BASE/XCKU060 Top View ............................................................................................. 1
Figure 2
ADM-SDEV-BASE/XCKU060 Block Diagram .................................................................................... 4
Figure 3
LED Locations ................................................................................................................................... 6
Figure 4
JTAG Boundary Scan Chain .............................................................................................................. 7
Figure 5
Clocks ................................................................................................................................................ 8
Figure 6
Flash Address Map .......................................................................................................................... 11
Figure 7
MGT Links ....................................................................................................................................... 16
Figure 8
DRAM Banks ................................................................................................................................... 17
