ADM-SDEV-BASE/XCKU060 User Manual
V1.0 - 27th November 2018
•
-loadbit "up 0x0000000 <directory/to/file/filename.bit>" (0th location)
•
-loadbit "up 0x2000000 <directory/to/file/filename.bit>" (1st location, optional)
Program with vivado hardware manager with these settings (see xapp1233):
•
SPI part: mt25qu256-spi-x1_x2_x4_x8
•
State of non-config mem I/O pins: Pull-none
•
Target the four files generated from the write_cfgmem tcl command.
3.4.2 Configuration via JTAG
A Xilinx Platform Programming Cable may be attached to the programming header on the Config FMC board.
This permits the FPGA to be reconfigured using the Xilinx Vivado Hardware Manager via JTAG. The device will
be automatically recognized in Vivado Hardware Manager.
For more detailed instructions, please see “Programming the FPGA Device” section of Xilinx UG908: https://
www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug908-vivado-programming-debugging.pdf
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Functional Description
ad-ug-1360_v1_0.pdf
