Alinx ZYNQ UltraScale+, User Manual, Page: 53 / 66

ZYNQ Ultr FPGA Board AXU5EV-P User Manual
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PCIE_RX1_N 224_RX3_N P1 PCIE Channel 1 Data Receive Negative
PCIE_RX1_P 224_RX3_P P2 PCIE Channel 1 Data Receive Positive
PCIE_TX0_N 224_TX2_N R3 PCIE Channel 0 Data Transmit Negative
PCIE_TX0_P 224_TX2_P R4 PCIE Channel 0 Data Transmit Positive
PCIE_TX1_N 224_TX3_N N3 PCIE Channel 1 Data Transmit Negative
PCIE_TX1_P 224_TX3_P N4 PCIE Channel 1 Data Transmit Positive
PCIE_PERST B43_L8_N AC11 PCIE Board Reset Signal
Part 3.12: CAN Communication Interface
There are 2 CAN communication interfaces on the AXU5EV-P carrier
board, which are connected to the MIO interface of the BANK501 on the PS
system side. The CAN transceiver chip selected TI's SN65HVD232C chip for
user CAN communication services. The connection of the CAN transceiver
chip on the PS side is show as Figure 3-12-1
Figure 3-12-1: Connection diagram of CAN transceiver chip on PS side
The CAN communication pin assignments are as follows:
Signal Name ZYNQ Pin Name ZYNQ Pin Number Description
PS_CAN1_TX PS_MIO32 J16 CAN1 Transmitter
PS_CAN1_RX PS_MIO33 L16 CAN1 Receiver