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ZYNQ Ultr FPGA Board AXU5EV-P User Manual
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USB Interface Pin Assignment:
Signal Name
Pin Name
Pin Number
Description
USB_SSTXP
505_TX1_P
D23
USB3.0 Data Transmit Positive
USB_SSTXN
505_TX1_N
D24
USB3.0 Data Transmit Negative
USB_SSRXP
505_RX1_P
D27
USB3.0 Data Receive Positive
USB_SSRXN
505_RX1_N
D28
USB3.0 Data Receive Negative
USB_DATA0
PS_MIO56
C16
USB2.0 Data Bit0
USB_DATA1
PS_MIO57
A16
USB2.0 Data Bit1
USB_DATA2
PS_MIO54
F17
USB2.0 Data Bit2
USB_DATA3
PS_MIO59
E17
USB2.0 Data Bit3
USB_DATA4
PS_MIO60
C17
USB2.0 Data Bit4
USB_DATA5
PS_MIO61
D17
USB2.0 Data Bit5
USB_DATA6
PS_MIO62
A17
USB2.0 Data Bit6
USB_DATA7
PS_MIO63
E18
USB2.0 Data Bit7
USB_STP
PS_MIO58
F18
USB2.0 Stop Signal
USB_DIR
PS_MIO53
D16
USB2.0 Data Direction Signal
USB_CLK
PS_MIO52
G18
USB2.0 Clock Signal
USB_NXT
PS_MIO55
B16
USB2.0 Next Data Signal
USB_RESET_N
PS_MIO31
H16
USB2.0 Reset Signal
Part 3.5: Gigabit Ethernet Interface
There are 2 Gigabit Ethernet ports on the AXU5EV-P carrier board, one is
connected to the PS end, and the other is connected to the PL end. The GPHY
chip uses Micrel's KSZ9031RNX Ethernet PHY chip to provide users with
network communication services. The KSZ9031RNX chip supports
10/100/1000 Mbps network transmission rate, and communicates with the
MAC layer of the ZU4EV system through the RGMII interface. KSZ9031RNX
supports MDI/MDX adaptation, various speed adaptation, Master/Slave
adaptation, and MDIO bus for PHY register management.
When the KSZ9031RNX is powered on, it will detect the level status of
some specific IOs to determine its own operating mode. Table 3-5-1 describes
the default settings after the GPHY chip is powered on.