Alinx AXU2CGA, User Manual

Page: 16 / 29

ZYNQ Ultr FPGA Board AXU2CGA/B User Manual
16 / 29
Amazon Store: https://www.amazon.com/alinx
505_USB_CLKP PS_MGTREFCLK2P_505 E21
USB3.0 Reference Clock
Positive
505_USB_CLKN PS_MGTREFCLK2N_505 E22
USB3.0 Reference Clock
Negative
USB_DATA0 PS_MIO56 C16 USB2.0 Data Bit0
USB_DATA1 PS_MIO57 A16 USB2.0 Data Bit1
USB_DATA2 PS_MIO54 F17 USB2.0 Data Bit2
USB_DATA3 PS_MIO59 E17 USB2.0 Data Bit3
USB_DATA4 PS_MIO60 C17 USB2.0 Data Bit4
USB_DATA5 PS_MIO61 D17 USB2.0 Data Bit5
USB_DATA6 PS_MIO62 A17 USB2.0 Data Bit6
USB_DATA7 PS_MIO63 E18 USB2.0 Data Bit7
USB_STP PS_MIO58 F18 USB2.0 Stop Signal
USB_DIR PS_MIO53 D16 USB2.0 Data Direction Signal
USB_CLK PS_MIO52 G18 USB2.0 Clock Signal
USB_NXT PS_MIO55 B16 USB2.0 the NEXT Data Signal
Part 9: Gigabit Ethernet Interface
There is 1 Gigabit Ethernet interface on AXU2CGA/B, and the Ethernet
interface is on BANK502 of PS connected through GPHY chip. The GPHY chip
uses the KSZ9031RNXIC Ethernet PHY chip from Micrel, and the PHY
Address is 001. Figure 9-1 is a schematic diagram of the connection of the
Ethernet PHY chip on the ZYNQ PS side:
Figure 9-1: ZYNQ PS System and GPHY Schematic