ARTIX-7 FPGA Development Board AX7103 User Manual
51 / 55
www.alinx.com
Figure 3-11-2: XADC Connector Schematic
Figure 3-11-3: XADC Connector on the Carrier board
XADC Pin Assignment
XADC
Interface
FPGA Pin
Input amplitude
Description
1
，
2
VP_0 : L10
VN_0 : M9
Peak to peak 1V
FPGA-specific XADC input channel
5
，
6
AD9P : J15
AD9N : H15
Peak to peak 1V FPGA-assisted XADC input channel 9
(can be used as normal IO)
9
，
10
AD0P : H13
AD0N : G13
Peak to peak 1V FPGA-assisted XADC input channel 0
(can be used as normal IO)
Part 3.12: keys
The AX7103 FPGA carrier board contains two user keys KEY1~KEY2. All
keys are connected to the normal IO of the FPGA. The key is active low. When
the key is pressed, the IO input voltage of the FPGA is low. When no key is
pressed, The IO input voltage of the FPGA is high. The circuit of the key part is
shown in Figure 3-12-1.