ARTIX-7 FPGA Development Board AX7103 User Manual
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The JTAG interface J1 on AC7100B FPGA core board uses a 6-pin
2.54mm pitch single-row test hole. If you need to use the JTAG connection to
debug on the core board, you need to solder a 6-pin single-row pin header.
Figure 2-8-2 shows the JTAG interface J1 on the AC7100B FPGA core board.
Figure 2-8-2: JTAG Interface on Core Board
Part 2.9: Power Interface on the Core Board
In order to make the AC7100B FPGA core board work alone, the core
board reserve a 2 PIN interface (J3), and power the core board separately by
connecting a 5V power supply. Among them, PIN1 pin is connected to +5V,
PIN2 pin is grounded, and the positive and negative pins should not be
connected wrongly.
Figure 2-9-1: J3 interface schematic