ARTIX-7 FPGA Development Board AX7103 User Manual
15 / 55
www.alinx.com
Part 2.4: DDR3 DRAM
The FPGA core board AC7100B is equipped with two Micron 4Gbit
(512MB) DDR3 chips, model MT41J256M16HA-125 (compatible with
MT41K256M16HA-125). The DDR3 SDRAM has a maximum operating speed
of 800MHz (data rate 1600Mbps). The DDR3 memory system is directly
connected to the memory interface of the BANK 34 and BANK35 of the FPGA.
The specific configuration of DDR3 SDRAM is shown in Table 2-4-1.
Bit Number
Chip Model
Capacity
Factory
U5,U6
MT41J256M16HA-125
256M x 16bit
Micron
Table 2-4-1: DDR3 SDRAM Configuration
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3. The hardware
connection diagram of DDR3 DRAM is shown in Figure 2-4-1:
Figure 2-4-1: The DDR3 DRAM Schematic