The PCM bus is for audio data.
The PCM Interface on the AP6256 can connect to linear PCM Codec devices in master or slave
mode. In master mode, the AP6256 generates the PCM_CLK and PCM_SYNC signals, and in
slave mode, these signals are provided by another master on the PCM interface and are inputs to
the AP6256.
The configuration of the PCM interface may be adjusted by the host through the use of
vendor-specific HCI commands.
SDIO interface is for WLAN function.
BTWDB module supports SDIO V3.0 for all 1.8V 4-bit UHSI speeds: SDR50(100Mbps),
SDR104(208MHz) and DDR50(50MHz, dual rates) in addition to the 3.3V d efault
speed(25MHz) and high speed (50 MHz). It has the ability to stop the SDIO clock and map the
interrupt signal into a GPIO pin. This ‘out-of-band’ interrupt signal notifies the host when the WLAN
device wants to turn on the SDIO interface. The ability to force the control of the gated clocks from
within the WLAN chip is also provided.
Function 0 Standard SDIO function (Max Block Size / Byte Count = 32B)
Function 1 Backplane Function to access the internal System On Chip (SOC) address
space (Max Block Size / Byte Count = 64B)
Function 2 WLAN Function for efficient WLAN packet transfer through DMA (Max Block
Size/Byte Count=512B)
SDIO Pin Description
Summary of Contents for 8088
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