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[AKD4951AEN-B]

<KM121002>

2016/09

- 1 -

GENERAL DESCRIPTION

The AKD4951AEN-B is an evaluation board for the AK4951AEN 24bit CODEC with built-in PLL and
MIC/HP/SPK Amplifier. The AKD4951AEN-B has the interface with AKM’s A/D evaluation boards. Therefore,
it’s easy to evaluate the AK4951AEN. The AKD4951AEN-B also has the digital audio interface and can achieve
the interface with digital audio systems via opt-connector.

Ordering Guide

AKD4951AEN-B ---

Evaluation board for AK4951AEN

(Control software is included in this package.)

FUNCTION

Compatible with 2 types of interface

- Direct interface with AKM’s A/D converter evaluation boards
- DIT/DIR with optical input/output

USB port for board control

Mini

Jack

Digital

MIC

TVDD DVDD AVDD SVDD

REG

3.3V

1.8V

3.3V

3.3V

3.3V

GND1

0V

HP

Jack

REG1

5V

SPK

SPP SPN

LINE-

OUT

Jack

AK4951AEN

Opt In

Opt Out

PIC4550

AK4118A
(DIT/DIR)

External

Clock

LIN1

RIN1

LIN2

RIN2

LIN3

RIN3

USB

LDO

(T3)

1.8V

REG

Figure 1. AKD4951AEN-B Block Diagram

* Circuit diagram and PCB layout are attached at the end of this manual.

Evaluation board Rev.2 for AK4951AEN

AKD4951AEN-B

Summary of Contents for AKD4951AEN-B

Page 1: ...B Evaluation board for AK4951AEN Control software is included in this package FUNCTION Compatible with 2 types of interface Direct interface with AKM s A D converter evaluation boards DIT DIR with opt...

Page 2: ...ground Table 1 Set up of power supply lines 1 2 In case of using the power supply connectors JP3 SVDD JP17 USB5V 1 8V 5V 3 3V 2 Set up the evaluation mode jumper pins and DIP switch See the followings...

Page 3: ...A supports 256fs and 512fs When evaluating in a condition except above please use other mode Refer to the datasheet for register setting of the AK4951AEN Applicable Evaluation Mode 1 A D Evaluation us...

Page 4: ...8A and SDTO of the AK4951AEN is output to the AK4118A The jumper pins should be set as follows JP11 MCKI JP14 BICK JP12 LRCK DIR EXT DIR EXT JP15 DIR EXT SDTO 2 Evaluation of D A using DIR of AK4118A...

Page 5: ...The master clock is input from the MCKI pin of JP11 An internal PLL circuit generates BICK and LRCK Registers of the AK4951AEN should be set to PLL Master Mode BICK LRCK SDTI and SDTO are input into a...

Page 6: ...1AEN is generated by an internal PLL circuit Registers of the AK4951AEN should be set to PLL Slave Mode Reference Clock BICK BICK LRCK SDTI and SDTO are input into and output from JP14 JP12 JP13 and J...

Page 7: ...EN DSP or P MCKI BICK LRCK SDTO SDTI BCLK LRCK SDTI SDTO 1fs 32fs MCLK 256fs 384fs 512fs or 1024fs Figure 4 EXT Slave Mode 4 Evaluation in Loop back Mode 4 1 Setting in PLL Master Mode Do not connect...

Page 8: ...k The jumper pins should be set as follows JP11 MCKI JP15 DIR EXT DIR EXT JP13 SDTO SDTI DIR ADC JP10 SDTI SEL 4 3 Setting in External Slave Mode Registers of the AK4951AEN should be set to EXT Slave...

Page 9: ...O 64fs O 3 0 1 1 24bit Left justified 24bit Right justified H L O 64fs O 4 1 0 0 24bit Left justified 24bit Left justified H L O 64fs O Default 5 1 0 1 24bit I2 S 24bit I2 S L H O 64fs O 6 1 1 0 24bi...

Page 10: ...Figure 5 LIN1 RIN1 LIN2 RIN2 LIN3 RIN3 Input Circuits 1 1 LIN1 RIN1Input Circuit Default LIN1 and RIN1are input to J1 When the Mic Power is not used JP6 and JP7 should be set to open JP4 JP5 JP2 RIN...

Page 11: ...used JP8 and JP9 should be set to open JP8 JP9 JP2 RIN SEL JP1 LIN SEL LIN3 LIN2 LIN1 RIN3 RIN2 RIN1 MP RIN2 MP LIN2 1 3 LIN3 RIN3 Input Circuit LIN3 and RIN3 are input to J2 and J3 JP2 RIN SEL JP1 LI...

Page 12: ...e output from J2 2 2 SPP SPN Output Circuit TP2 SPN 1 TP1 SPP 1 SPN SPP Figure 7 SPP SPN Output Circuit SPP and SPN are output from TP1 and TP2 2 3 Stereo Line Output Circuit J3 LINE OUT 1 2 3 C25 1u...

Page 13: ...evaluation board and PC with a USB cable 3 The USB control is recognized as HID Human Interface Device on the PC 4 Double click the icon akd4951aen b exe to open the control program Note 1 5 When the...

Page 14: ...egisters 3 All Write Executes write commands for all registers displayed 4 All Read Executes read commands for all registers displayed 5 Save Save Address of Register dialog box pops up 6 Load Execute...

Page 15: ...When other button is clicked the setting dialog opens Refer to the Sequential process section for details of each dialog box setting or Dialog Box section for details of each dialog box setting Figur...

Page 16: ...reo DMDAT SDTO DMDAT Digital Filter SDTO When Digital MIC used LIN1 changes to DMDAT Playback_Headphone Headphone Output SDTI LOUT ROUT SDTI DAC HPL HPR Playback_Speaker ALC ON SPK Output SDTI SPP SPN...

Page 17: ...o I F dialog box MIC ADC Setting button Opens MIC_ADC Setting dialog box Digital MIC Setting button Opens Digital MIC Setting dialog box Digital Filter button Opens Filter Setting dialog box ALC Setti...

Page 18: ...mouse operation Button Down indicates 1 and the bit name is shown in red when read only the name is shown in dark red Button Up indicates 0 and the bit name is shown in blue when read only the name is...

Page 19: ...x is not checked the data will become 0 Click OK to write the set values to the registers or click Cancel to cancel this setting Figure 14 Register Set Window 2 2 Read Data Read Click the Read button...

Page 20: ...check box When the All Address checkbox is checked all register settings will be saved Start Address edit box When the All Address check box is not checked set starts register address to save End Add...

Page 21: ...file assignment mar Close button Closes the dialog box and finish the process All Write flame Executes all register write Selected files are executed in descending order Start button Start the registe...

Page 22: ...this dialog box Figure 17 Sequence Window Sequence Setting Set register sequence according to the following process 1 Select a command Use Select pull down box to choose commands Corresponding boxes...

Page 23: ...are shown below No use None Register Address Data Interval Reg_Mask Address Data Mask Interval Interval Interval Stop None End None Control Buttons Functions of Control Button are shown below DEL but...

Page 24: ...Selected files are executed in descending order Stop button Stops the sequence process Help button Opens a help window Save button Saves a sequence setting file assignment The file name is mas Open ri...

Page 25: ...io I F setting dialog The settings on this dialog are interlocked with the settings on register map Refer to the datasheet for register definitions Figure 20 System Clock Audio I F Window When clock m...

Page 26: ...cked with the settings on register map Refer to the datasheet for register demotions Figure 21 MIC ADC Setting Window In the following cases PMVCM bit is set to 1 automatically Since PMVCM bit is not...

Page 27: ...ital MIC Setting button in the main window to open Digital MIC setting dialog The settings on this dialog are interlocked with the settings on register map Refer to the datasheet for register definiti...

Page 28: ...alog Filter Plot Register writes of a filter factor are also executed Write button Calculation of all the filters and coefficient writing are executed Reg Map to Fc Plot check box When Reg Map to Fc P...

Page 29: ...election of filter type LPF or HPF Gain Gain 10dB Gain 0dB EQ0 Pole Frequency EQ0 Pole frequency 0 0001 fc fs 0 497 Zero point Frequency EQ0 Zero point frequency 0 0001 fc fs 0 497 Gain Gain 20dB Gain...

Page 30: ...layed and a calculation of register setting is not carried out Figure 26 Register Setting for Filter Window Followings are the cases when a register set value is updated 1 When Register Setting button...

Page 31: ...w Frequency Range edit box The width of the frequency display is specified UpDate button It draws in the graph again Gain Phase radio button Switch of Gain Phase display Log View check button Switch o...

Page 32: ...s operated with the mouse and it is possible to set the filter characteristic on this screen The center frequency and the gain setting are changed by moving the mouse while left clicking The setting o...

Page 33: ...ch Level R ch Level Gain mismatch of stereo MIC sensitivity are set Distance The distance between the sound source and the MIC is set Angle The angle between the sound source and the MIC is set Defaul...

Page 34: ...c correction function is effective and only EQ of 1 is effective Figure 32 This automatic compensation is effective to EQ which set the gain as 1 Note 5 Note 5 There is a possibility that the automati...

Page 35: ...setup is returned the state of before pushing a button Please use the button when it expected that a noise continues Figure 33 Equalizer Gain Setting Button ON EQCx bit OFF EQxG5 0 bits 0x3F 0 03dB E...

Page 36: ...Refer to the datasheet for register definitions Figure 36 ALC Setting Window Volume Read When the Start button on the bottom right of the dialog is clicked reading VOL register is executed periodicall...

Page 37: ...re 38 DAC Setting Window In the following cases PMVCM bit is set to 1 automatically Since PMVCM bit is not set to 0 even if it returns each setup please operate a register map directly When DAC Power...

Page 38: ...dialog The settings on this dialog are interlocked with the settings on register map Refer to the datasheet for register definitions Figure 39 BEEP Setting Window When BEEP Input Power PMBP bit is Po...

Page 39: ...Recording_MIC 18dB ALC AHPF ON When Recording_MIC 18dB button in the main window is clicked the sequence for MIC input Settings stereo is executed Note 7 MIC ADC Setting Window ALC Setting Window Filt...

Page 40: ...IC AHPF ALC ON When Recording_DigitalMIC button in the main window is clicked the sequence for Digital MIC input Settings stereo is executed Note 7 Digital MIC Setting Window ALC Setting Window Filter...

Page 41: ...eadphone output Settings is executed DAC_LINE SPK HP Setting Window Figure 42 Playback_Headphone Setting 4 Playback_Speaker ALC ON When Playback_Speaker button in the main window is clicked the sequen...

Page 42: ...is clicked the sequence for Line output Settings is executed Note 7 DAC_LINE SPK HP Setting Window Figure 44 Playback_Lineout Setting 5 Loopback_Headphone When Loopback_Lineout button in the main wind...

Page 43: ...Window Figure 45 Loopback_Headphone Setting Note 7 The register setting of ALC by the sequence of Recording_MIC 18dB Recording_DigitalMIC Playback_Speaker or Loopback_Headphone is same The register se...

Page 44: ...MGAIN 18dB S N D 1dBFS 82 6 82 6 dB DR 60dBFS A Weighted 89 3 89 4 dB S N A weighted 89 3 89 4 dB MGAIN 0dB S N D 1dBFS 83 5 83 5 dB DR 60dBFS A Weighted 96 0 96 0 dB S N A weighted 96 0 96 0 dB 2 DAC...

Page 45: ...tor MGAIN 18dB AK4951AEN ADC FFT 1dBFS 140 0 120 100 80 60 40 20 d B F S 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 46 FFT Input level 1dBFS AK4951AEN ADC FFT 60dBFS 140 0 120 100 80 60 40 20 d B F...

Page 46: ...o signal 140 0 120 100 80 60 40 20 d B F S 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 48 FFT No signal AK4951AEN ADC THD N vs Input Level fin 1kHz 100 60 95 90 85 80 75 70 65 d B F S 100 0 90 80 70...

Page 47: ...Frequency 1dBFS 100 60 95 90 85 80 75 70 65 d B F S 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 50 THD N vs Input Frequency AK4951AEN ADC Linearity fin 1kHz 100 0 90 80 70 60 50 40 30 20 10 d B F S...

Page 48: ...B 20 20k 50 100 200 500 1k 2k 5k 10k Hz T TT T T T T T T TT T T T T T T T T T TT T TT T T T T T T T T T T T T T T T T T T T Figure 52 Crosstalk AK4951AEN ADC Frequency Response 1dBFS 2 0 1 8 1 6 1 4...

Page 49: ...EN ADC FFT 1dBFS 20 20k 50 100 200 500 1k 2k 5k 10k Hz 140 0 120 100 80 60 40 20 d B F S Figure 54 FFT Input level 1dBFS AK4951AEN ADC FFT 60dBFS 20 20k 50 100 200 500 1k 2k 5k 10k Hz 140 0 120 100 80...

Page 50: ...o signal 20 20k 50 100 200 500 1k 2k 5k 10k Hz 140 0 120 100 80 60 40 20 d B F S Figure 56 FFT No signal AK4951AEN ADC THD N vs Input Level fin 1kHz 100 0 90 80 70 60 50 40 30 20 10 dBr 100 60 95 90 8...

Page 51: ...Frequency 1dBFS 20 20k 50 100 200 500 1k 2k 5k 10k Hz 100 60 95 90 85 80 75 70 65 d B F S Figure 58 THD N vs Input Frequency AK4951AEN ADC Linearity fin 1kHz 100 0 90 80 70 60 50 40 30 20 10 dBr 100...

Page 52: ...200 500 1k 2k 5k 10k Hz 140 60 130 120 110 100 90 80 70 d B T T T TT T T T T T T T T T T TTTT T T T T T T Figure 60 Crosstalk AK4951AEN ADC Frequency Response 1dBFS 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k...

Page 53: ...tor MGAIN 18dB AK4951AEN ADC FFT 1dBFS 140 0 120 100 80 60 40 20 d B F S 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 62 FFT Input level 1dBFS AK4951AEN ADC FFT 60dBFS 140 0 120 100 80 60 40 20 d B F...

Page 54: ...o signal 140 0 120 100 80 60 40 20 d B F S 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 64 FFT No signal AK4951AEN ADC THD N vs Input Level fin 1kHz 100 0 90 80 70 60 50 40 30 20 10 dBr 100 60 95 90 8...

Page 55: ...Frequency 1dBFS 20 20k 50 100 200 500 1k 2k 5k 10k Hz 100 60 95 90 85 80 75 70 65 d B F S Figure 66 THD N vs Input Frequency AK4951AEN ADC Linearity fin 1kHz 100 0 90 80 70 60 50 40 30 20 10 dBr 100...

Page 56: ...5k 10k Hz 140 60 130 120 110 100 90 80 70 d B TTT T T T T T T T TT TT T T T TT T T T T T T TT T T T T T T T TTT T TT Figure 68 Crosstalk AK4951AEN ADC Frequency Response 1dBFS 2k 20k 4k 6k 8k 10k 12k...

Page 57: ...EN ADC FFT 1dBFS 20 20k 50 100 200 500 1k 2k 5k 10k Hz 140 0 120 100 80 60 40 20 d B F S Figure 70 FFT Input level 1dBFS AK4951AEN ADC FFT 60dBFS 20 20k 50 100 200 500 1k 2k 5k 10k Hz 140 0 120 100 80...

Page 58: ...o signal 20 20k 50 100 200 500 1k 2k 5k 10k Hz 140 0 120 100 80 60 40 20 d B F S Figure 72 FFT No signal AK4951AEN ADC THD N vs Input Level fin 1kHz 100 0 90 80 70 60 50 40 30 20 10 dBr 100 60 95 90 8...

Page 59: ...Frequency 1dBFS 20 20k 50 100 200 500 1k 2k 5k 10k Hz 100 60 95 90 85 80 75 70 65 d B F S Figure 74 THD N vs Input Frequency AK4951AEN ADC Linearity fin 1kHz 100 0 90 80 70 60 50 40 30 20 10 dBr 100...

Page 60: ...100 200 500 1k 2k 5k 10k Hz 140 60 130 120 110 100 90 80 70 d B T T T T T T T T T T TT T TT TT T T Figure 76 Crosstalk AK4951AEN ADC Frequency Response 1dBFS 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k Hz 2...

Page 61: ...K4951AEN DAC HP FFT 0dBFS 20 20k 50 100 200 500 1k 2k 5k 10k Hz 140 0 120 100 80 60 40 20 d B r A Figure 78 FFT Input level 0dBFS AK4951AEN DAC HP FFT 60dBFS 20 20k 50 100 200 500 1k 2k 5k 10k Hz 140...

Page 62: ...o signal 20 20k 50 100 200 500 1k 2k 5k 10k Hz 140 0 120 100 80 60 40 20 d B r A Figure 80 FFT No signal AK4951AEN DAC HP FFT Out of band Noise 140 0 120 100 80 60 40 20 d B r A 20 100k 50 100 200 500...

Page 63: ...Level fin 1kHz 120 40 110 100 90 80 70 60 50 d B r A 120 0 100 80 60 40 20 dBFS Figure 82 THD N vs Input Level AK4951AEN DAC HP THD N vs Frequency 0dBFS 120 40 110 100 90 80 70 60 50 d B r A 20 20k 5...

Page 64: ...HP Linearity fin 1kHz 100 0 90 80 70 60 50 40 30 20 10 d B r A 100 0 90 80 70 60 50 40 30 20 10 dBFS Figure 84 Linearity AK4951AEN DAC HP Crosstalk 0dBFS 120 40 110 100 90 80 70 60 50 d B 20 20k 50 1...

Page 65: ...AKD4951AEN B KM121002 2016 09 65 AK4951AEN DAC HP Frequency Response 0dBFS 0 5 0 5 0 4 0 3 0 2 0 1 0 0 1 0 2 0 3 0 4 d B r A 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k Hz Figure 86 Frequency Response...

Page 66: ...SKP FFT 0 5dBFS SPKG 01 140 0 120 100 80 60 40 20 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 87 FFT Input level 0 5dBFS AK4951AEN DAC SKP FFT 60dBFS SPKG 01 140 0 120 100 80 60 40 20 d B r...

Page 67: ...al SPKG 01 140 0 120 100 80 60 40 20 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 89 FFT No signal AK4951AEN DAC SKP Out of band noise SPKG 01 140 0 120 100 80 60 40 20 d B r A 20 100k 50 100...

Page 68: ...0 5dBFS SPKG 01 120 40 110 100 90 80 70 60 50 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 91 THD N vs Input Frequency AK4951AEN DAC SKP Linearity 0 5dBFS SPKG 01 100 0 90 80 70 60 50 40 30 2...

Page 69: ...5 0 4 0 3 0 2 0 1 d B r A 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k Hz Figure 93 Frequency Response AK4951AEN DAC SKP THD N vs Output Power fin 1kHz SPKG 00 0 200m 20m 40m 60m 80m 100m 120m 140m 160m 180m...

Page 70: ...50m W 100 40 90 80 70 60 50 d B 40 0 35 30 25 20 15 10 5 dBFS Figure 95 THD N vs Output Power SPKG 01 AK4951AEN DAC SKP THD N vs Output Power fin 1kHz SPKG 10 0 500m 50m 100m 150m 200m 250m 300m 350m...

Page 71: ...AEN B KM121002 2016 09 71 AK4951AEN DAC SKP THD N vs Output Power fin 1kHz SPKG 11 0 1 2 200m 400m 600m 800m 1 W 120 0 100 80 60 40 20 d B 40 0 35 30 25 20 15 10 5 dBFS Figure 97 THD N vs Output Power...

Page 72: ...Line out FFT 0dBFS LVCM 01 140 0 120 100 80 60 40 20 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 98 FFT Input level 0dBFS AK4951AEN DAC Line out FFT 3dBFS LVCM 01 140 0 120 100 80 60 40 20 d...

Page 73: ...0dBFS LVCM 01 140 0 120 100 80 60 40 20 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 100 FFT Input level 60dBFS AK4951AEN DAC Line out FFT No signal LVCM 01 140 0 120 100 80 60 40 20 d B r A 2...

Page 74: ...01 140 0 120 100 80 60 40 20 d B r A 20 100k 50 100 200 500 1k 2k 5k 10k 20k 50k Hz Figure 102 FFT Out of band Noise AK4951AEN DAC Line out THD N vs Input Level fin 1kHz LVCM 01 120 60 110 100 90 80 7...

Page 75: ...cy 3dBFS LVCM 01 120 60 110 100 90 80 70 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 104 THD N vs Input Frequency AK4951AEN DAC Line out Linearity fin 1kHz LVCM 01 100 0 90 80 70 60 50 40 30...

Page 76: ...0 100 90 80 70 60 50 d B 20 20k 50 100 200 500 1k 2k 5k 10k Hz T T T T T TT T T T TT T TT T T T T Figure 106 Crosstalk AK4951AEN DAC Line out Frequency Response 3dBFS LVCM 01 4 2 3 8 3 6 3 4 3 2 3 2 8...

Page 77: ...M DD Manual Revision Board Revision Reason Page Contents 15 03 31 KM121000 0 First edition 16 03 10 KM121001 1 Board change 1 AK4951AEN Rev C Rev D Change 44 76 Measurement data were changed 16 09 20...

Page 78: ...AKM in writing 3 Though AKM works continually to improve the Product s quality and reliability you are responsible for complying with safety standards and for providing adequate designs and safeguard...

Page 79: ...22k R9 1k C32 10u C30 2 2u C10 1u C13 open T2 AP1154ADL33 NC 8 Vin 7 Vcont 6 NC 5 NC 1 Vout 2 PCL 3 GND 4 R14 51 JP3 SVDD R3 5 1 R33 open C34 2 2u U1 AK4951AEN LIN3 1 RIN2 2 LIN2 3 MPWR2 4 MPWR1 5 RI...

Page 80: ...0 1u JP12 LRCK C47 0 47u U2 AK4118A IPS0 RX4 1 NC 2 DIF0 RX5 3 TEST2 4 DIF1 RX6 5 VSS1 6 DIF2 RX7 7 IPS1 IIC 8 P SN 9 XTL0 10 XTL1 11 TVDD 13 NC GP1 14 TX0 GP2 15 TX1 GP3 16 BOUT GP4 17 COUT GP5 18 UO...

Page 81: ...0 1u R32 0 R31 0 R29 1k C65 0 47u JP16 PIC 1 2 3 4 5 C50 0 1u PORT3 USB Connector VBUS 1 D 2 D 3 ID 4 GND 5 R26 100k U3 PIC18F4550 RC7 RX DT SDO 1 RD4 SPP4 2 RD5 SPP5 P1B 3 RD6 SPP6 P1C 4 RD7 SPP7 P1...

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