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APE1553-1/2(-DS) Hardware Manual

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STRUCTURE OF THE APE1553-1/-2

The structure of the APE1553 card is shown in the block diagram.

The APE1553-1/-2 comprises the following main sections:



PCI Express Interface and BIU-IO FPGA



Global RAM



BIU Section

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Physical I/O Interface with up to two Dual redundant MIL-STD-1553 busses



IRIG – Time Code Processor

Figure 3-1 Block Diagram of APE1553-1/-2

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Summary of Contents for APE1553-1-DS

Page 1: ...al APE1553 1 2 DS Single Dual Stream MIL STD 1553 PCI Express Card AIM GmbH Sasbacher Str 2 79111 Freiburg Germany Tel 49 761 45229 0 Fax 49 761 45229 33 sales aim online com www aim online com May 2015 V01 01 Rev B ...

Page 2: ......

Page 3: ...i APE1553 1 2 DS Hardware Manual for Single Dual Stream MIL STD 1553 PCI Express Card V01 01 Rev B May 2015 AIM No 60 111Dx 16 0101 B ...

Page 4: ... PA 19053 267 982 2600 877 520 1553 salesusa aim online com AIM UK Cressex Business Park Lincoln Rd High Wycombe Bucks HP12 3RB England 44 1494 44 68 44 salesuk aim online com Notice The information that is provided in this document is believed to be accurate No responsibility is assumed by AIM for its use No license or rights are granted by implication in connection therewith Specifications are s...

Page 5: ...rections V01 00 Rev C 21 09 2011 F Scherer Some extensions V01 00 Rev D 10 11 2011 F Scherer Table for B2B connector 5V and 3 3V removed V01 01 Rev A 07 04 2015 F Scherer Some corrections Change the Word Format Template Re Formatting MILScope section included to UM V01 01 Rev B 13 05 15 B Schweitzer Minor corrections at chapter 3 1 5 and fix formatting problems ...

Page 6: ...nd BIU I O FPGA 16 3 1 1 PCI Express Bus Interface 16 3 1 2 Global RAM Interface and Arbitration 16 3 1 3 SPI Controller for SPI Flash update programming 16 3 1 4 MIL STD 1553 Encoder 16 3 1 5 MIL STD 1553 Decoder 16 3 1 6 IRIG B Encoder Decoder and Timecode Processor TCP 17 3 1 7 Maintenance RS232 Interface 17 3 1 8 External Trigger Inputs and Outputs 17 3 1 9 User programmable General Purpose Di...

Page 7: ...3 Figure 2 5 1 LED description 14 Figure 3 1 Block Diagram of APE1553 1 2 15 Figure 3 4 1 MILbus Coupling Modes 19 Figure 3 4 2 MILbus Amplitude vs DAC value 20 Figure 4 1 1 Structure of the MILScope 21 Figure 4 2 2 MilScope coupling modes 22 LIST OF TABLES Table 2 3 1 1 Pinout DSUB9 Frontpanel Connector 4 Table 2 3 2 1 Pinout HD DSUB26 Frontpanel Connector 5 Table 2 3 2 4 1 RS232 connection 11 Ta...

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Page 9: ...rd with a resolution of 1us Transformer Direct Network Emulation and Isolated Coupling Modes are available at the external interface connector A standard breakout cable 2 0 m is available for the APE1553 card from DSUB9 connector to four two if APE1553 1 module PL 75 Twinax Connectors The hardware architecture provides enough resources i e processing capability and memory to guarantee that all spe...

Page 10: ...referenced herein In the event of conflict between the documents referenced and the contents of this document the contents of this document shall have precedence 1 3 1 Industry Documents MIL STD 1553B Department of Defence Interface Standard for Digital Time Division Command Response Multiplex Data Bus Notice 1 4 January 1996 PCI Express BUS Specification PCI SIG Revision 1 1 1 3 2 Product Specifi...

Page 11: ...system Please follow the instructions carefully to avoid any damage on the device To Install the Module 1 Shutdown your system and all peripheral devices 2 Unplug the power cord from the wall outlet Inserting or removing modules with power applied may result in damage to module devices 3 Remove the system cover to gain access to the system slots 4 Find a free PCIe slot in your system 5 Remove the ...

Page 12: ...onnector at the front panel Pin No Signal Description 1 MILbus Channel 1 Primary true APE1553 1 2 2 MILbus Channel 1 Primary complement APE1553 1 2 3 Shield 4 MILbus Channel 1 Secondary true APE1553 1 2 5 MILbus Channel 1 Secondary complement APE1553 1 2 6 MILbus Channel 2 Primary true APE1553 2 only 7 MILbus Channel 2 Primary complement APE1553 2 only 8 MILbus Channel 2 Secondary true APE1553 2 o...

Page 13: ...10 RS232 TXD 11 Trigger Output RT Channel 1 12 Trigger Input RT Channel 1 13 Trigger Output RT Channel 2 APE1553 2 only 14 Trigger Input RT Channel 2 APE1553 2 only 15 General Purpose Discrete Input Output 2 GPIO2 16 General Purpose Discrete Input Output 3 GPIO3 17 GND 18 General Purpose Discrete Input Output 4 GPIO4 19 Trigger Output BM Channel 1 20 Trigger Input BM Channel 1 21 Trigger Output BM...

Page 14: ...hronization requirement No connection required Case 3 Single or multiple AIM Module s with external IRIG B source Connect external IRIG B source to IRIG IN and GND of all modules Case 4 Multiple AIM Modules with no external IRIG B source internally synchronized Connect the IRIG OUT signal and the GND of the module you have chosen as the time master to all IRIG IN signals including the time master ...

Page 15: ...aster Mode IRIG Master Mode IRIG output J0504 has to be set to position 1 and 2 IRIG Slave Mode IRIG Input J0504 has to be set to position 2 and 3 or jumper uninstalled If set to IRIG Master Mode the on board generated IRIG output signal is available simultaneously on the B2B connector and on the frontpanel of the 1553 Physical Bus Interface board 1553 PBI To receive an external IRIG signal either...

Page 16: ...hen a user specific voltage is connected to a Discrete I O Figure 3 8 1 This serial resistor must limit the current through the open collector transistor to max 50 mA Otherwise the open collector transistor can be damaged EMC aspects are covered by filter circuitry All eight GPIO s are available on the ribbon cable B2B connector on the mainboard The GPIO s can be used as simple discrete inputs or ...

Page 17: ...screte I O Pin Ground FPGA Output Pin Discrete IO Pin Front Rear Connector APE1553 x Pulldown Resistor Current limiting Resistor 1 kOhm Onboard 5V Current limiting Resistor 10 kOhm Input Pin FPGA Ground Discrete output circuitry Discrete input circuitry ...

Page 18: ...10 APE1553 1 2 DS Hardware Manual Figure 3 2 2 3 2 Discrete Output protection Discrete IO Pin Front Rear Connector APE1553 x User Offboard User FPGA Output Pin Customized Discrete Rserial ...

Page 19: ...n link between the APE1553 and a PC COM Port the RS232 TXD RXD signals from the 26 pin high density DSUB Connector have to be connected with the RS232 TXD RXD signals from the PC via a NULL Modem connection PC RS232 Connector COM1 COM2 Module Connector Signal DSUB9 HD DSUB25 TXD 3 2 RXD 2 3 GND 5 7 Signal HD DSUB26 RXD 1 TXD 10 GND 17 Table 2 3 2 4 1 RS232 connection ...

Page 20: ...served Do not connect 2 Reserved Do not connect 3 ASL GPIO 1 GPIO 1 4 ASL GPIO 2 GPIO 2 5 ASL GPIO 3 GPIO 3 6 ASL GPIO 4 GPIO 4 7 ASL GPIO 5 GPIO 5 8 ASL GPIO 6 GPIO 6 9 ASL GPIO 7 GPIO 7 10 ASL GPIO 8 GPIO 8 11 Reserved Do not connect 12 IRIG Master Output Slave Input 13 GND 14 Reserved Do not connect 15 Reserved Do not connect 16 Reserved Do not connect Table 2 4 1 B2B connector Pinout For conne...

Page 21: ... can be connected together Pinout Figure 2 4 2 Example for a Ribbon Cable connection If there is a requirement to provide the B2B connector signals externally outside the PC an optional AIM Breakout Panel which occupies one PC Slot can be used to break out the signals The Breakout Panel is available on request please contact the factory Ribbon cable Ribbon cable I O Breakout Slot1 Slot4 Slot5 ...

Page 22: ...U 1 self test occurs COUPLED ACTIVITY 1 Green LED illuminates permanently if the MILbus channel 1 is connected LED flashes if any MILbus Activity is detected by the Encoder Decoder of the MILbus channel 1 FAIL2 Red LED illuminates if an Error during the BIU 2 self test occurs COUPLED ACTIVITY 2 Green LED illuminates permanently if the MILbus channel 2 is connected LED flashes if any MILbus Activit...

Page 23: ...553 card is shown in the block diagram The APE1553 1 2 comprises the following main sections PCI Express Interface and BIU IO FPGA Global RAM BIU Section Physical I O Interface with up to two Dual redundant MIL STD 1553 busses IRIG Time Code Processor Figure 3 1 Block Diagram of APE1553 1 2 ...

Page 24: ...erface port are implemented in the on board FPGA The Arbiter controls Global RAM access between the participants BIU Processors PCIe and the Timecode Processor in a fair arbitration scheme 3 1 3 SPI Controller for SPI Flash update programming The on board FPGA provides an IP Core SPI Controller to program update the on board SPI Flash memory 3 1 4 MIL STD 1553 Encoder The MIL STD 1553 encoder comp...

Page 25: ...s If no external IRIG signal is detected or if the synchronisation to the external IRIG signal gets lost the TCP switches automatically to the free wheeling operation mode As soon as an external IRIG B signal is detected in free wheeling mode the Time tag is automatically synchronized to this external IRIG B signal 3 1 7 Maintenance RS232 Interface The System and Maintenance Controller is used for...

Page 26: ...ted as a daughter board and is mounted on the APE1553 main board The Physical Bus Interface PBI contains one or two dual redundant MIL STD 1553 channels each channel comprises a dual redundant transceiver transmitter amplitude control circuitry a dual bus coupling transformer and the coupling relays with the MILbus network emulation circuitry The MIL STD 1553 dual trapezoidal transceivers allow fo...

Page 27: ...tion IN IN SH LG LG SH 23R 23R 23R 23R 23R In network emulation mode the MILbus emulation circuitry emulates a transformer coupled network without the use of MILbus couplers using a resistor network Thus an external dual redundant MIL STD 1553 Terminal can be directly connected to the module The Amplitude of the MILbus Signal can be controlled separately for the PRIMARY and SECONDARY channel To co...

Page 28: ... MILBus Amplitude Figure 3 4 2 MILbus Amplitude vs DAC value 3 5 Voltage Supplies All required on board supply voltages are either generated on board using switching power supplies or have to be provided by the System PC power supply The following System PC Power Supply Voltages are directly used by the module 3 3V 5 12 0V 5 NOTE Power Supply max tolerance should be less than 5 ...

Page 29: ...structure of the different MILScope parts Figure 4 1 1 Structure of the MILScope input amplifier 1 6 5 9 9 Pin D Sub female APX 1553 1 2 DS front panel status LEDs 1 10 19 9 18 26 26 Pin High Density D Sub direct transformer coupled network emulation direct channel 1 MILBus Transformer and Tranceiver TX Data RX Data MIL STD 1553 Encoder Decoder IO FPGA BIU processor coupling modes direct transform...

Page 30: ...g modes Primary Channel Secondary Channel measurement range 3VSS 30VSS Coupling Stub Extern TP measurement range 3VSS 30VSS Coupling Stub Extern TP ADC ADC K1 K4 K2 K5 K3 K6 The A DC has a resolution of 10Bit therefore a LSB in the 30VSS measurement range represents SS SS LSB mV V V 30 2 30 10 Whereas a LSB in the 3VSS measurement range represents SS SS LSB mV V V 3 2 3 10 It is possible to delay ...

Page 31: ... the trigger level higher than for a given time high pulse trigger event when the captured data is higher than the trigger level for a given time lower than for a given time low pulse trigger event when the captured data is lower than the trigger level for a given time Bus Monitor complex protocol trigger from the BIU Firmware Note The Trigger event might be delayed appr 10µs Trigger Channel ch A ...

Page 32: ...r measuring of any external analogue signals Table 4 3 1 Pinout External MILScope inputs Pin No Signal Pin No Signal Pin No Signal 1 RS232 RXD 10 RS232 TXD 19 Trigger Output BM ch 1 2 Trigger Output BC ch 1 11 Trigger Output RT ch 1 20 Trigger Input BM ch 1 3 Trigger Input BC ch 1 12 Trigger Input RT ch 1 21 Trigger Output BM ch 2 1 4 Trigger Output BC ch 2 1 13 Trigger Output RT ch 2 1 22 Trigger...

Page 33: ... redundant for PRI and SEC MILbus Response time support via eight bit timer with 250ns resolution Error Injection Parity error on selected word SYNC pattern definable on half bit basis on selectable word Manchester stuck at low or high error in selected word and bit position Gap error between selected words for 0 5 to 7 5 µs in 0 5µs steps Bit count error on selected word 3 bits Decoder For each B...

Page 34: ...time code processor is provided If no external IRIG B source is available a time code in IRIG B format is generated and can be used to synchronize multiple boards or modules Decoder Resolution 1 µs Width 1 Year 46 Bit Signal Waveform Amplitude modulated sine wave or square wave Modulation Ratio 3 1 to 6 1 Input Amplitude 0 5Vp p to 5Vp p Input Impedance 10k ohm Coupling AC coupled Time Jitter 5µs ...

Page 35: ...e External MILScope Channels A B Discrete I O Two user programmable Discrete I O s Input Output selection done by software Input High voltage 3 0V min 35 0V max Input Low voltage 0 0V min 0 8V max Output High voltage 4V appr Output Low voltage 0 4V max Max Sink Current of each open collector 100mA Please note When the default 5V for the discrete outputs are not used provide a serial resistor in li...

Page 36: ...1ms Trace before trigger 0 5242µs Vertical Functions Input Voltage coupling EXTERN30V voltage range 30VSS coupling EXTERN3V voltage range 3VSS coupling BUS30V voltage range 30VSS coupling BUS3V voltage range 3VSS Resolution 1 30mV 3mV 29 3mV 2 93mV Noise LSB Sampling rate 20ns 9LSB SNR 2 Sampling rate 20ns 41dB Bandwidth 3dB 3 Sampling rate 10ns 20MHz Sampling rate 20ns 15MHz Sampling rate 40ns 7 ...

Page 37: ...d 70Ohm Termination MILbus output Voltage appr 19Vpp Temperature 0 to 45 C Standard Operating 15 to 60 C Extended Temperature on request 40 to 85 C Storage Temperature Humidity 0 to 95 non condensing Voltage APE1553 2 APE1553 1 Working 1 idle Working 1 Idle 3 3V 2 9 W 2 8 W 2 8 W 2 8 W 12 0V 6 6 W 1 W 3 5 W 0 6 W Voltage APE1553 2 DS APE1553 1 DS Working 1 idle Working 1 Idle 3 3V 4 4 W 4 3 W 4 4 ...

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Page 39: ... Output IRIG B Inter Range Instrumentations Group Time code Format Type B I O Input Output JTAG Joint Test Action Group IEEE 1149 1 Boundary Scan LCA Logic Cell Array XILINX Programmable Gate Array LED Light emitting Diode MIL STD Military Standard MILbus MIL STD 1553 bus PBI Physical Bus Interface PROM Programmable Read Only Memory PC Personal Computer PCI Peripheral Component Interconnect PCIe P...

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