Ai-Thinker Technology ESP32-A1S, Manual, Page: 10 / 18

ESP32-A1S SoC module
Page 10of 18
Copyright © 2020 Shenzhen Ai-Thinker Technology Co., Ltd All Rights Reserved
Strapping Pin
Build-in LDO
(VDD_SDIO) voltage
Pin Default 3.3V 1.8V
MTDI/GPIO12 Pull down 0 1
System startup method
Pin Default SPI Flash startup method Download start mode
GPIO0 Pull up 1 0
GPIO2 Pull down / 0
Note: The working voltage of the built-in flash is 3.3V, and the MTDI needs to be pulled down or
left floating when powering on the chip with built-in flash
3. Function description
CPU and RAM
ESP32 contains two low-power Xtensa®32-bit LX6 MCUs. On-chip storage includes:

448KBytes ROM for program startup and kernel function call

520 KB on-chip SRAM for data and instruction storage

8KBytes of SRAM in RTC (RTC slow memory) can be accessed by the coprocessor in Deep-
sleep mode

The 8KBytes of SRAM in RTC, that is, RTC fast memory, can be used for data
storage and accessed by the main CPU during RTC startup in Deep-sleep mode

1kbit EFUSE, of which 256 bits are dedicated to the system (MAC address and chip
settings); the remaining 768 bits are reserved for user applications, which include
Flash encryption and chip ID
External Flash and SRAM
ESP32 supports up to four 16 MBytes external QSPI Flash and static random access memory
(SRAM), and has a hardware encryption function based on AES to protect developers’ programs
and data.

ESP32 accesses external QSPI Flash and SRAM through cache. Up to 16 MBytes of external
Flash is mapped to the CPU code space, supporting 8-bit, 16-bit and 32-bit access, and
executable code

Up to 8M Bytes of external Flash and SRAM are mapped to the CPU data space, supporting 8-
bit, 16-bit and 32-bit access. Flash only supports read operations, SRAM can support read and
write operations
Codec
AC101 is a highly integrated audio codec chip with high mixed signal integration. The
integrated digital phase-locked loop supports a wide range of input/output frequencies. It can
generate the audio clock required by the codec from the standard audio crystal rates of
22.5792MHz and 24.576MHz.

2 ADCs and 2 DACs @ 24 bits and interphase locked loop processing with flexible clocking
scheme

The signal-to-noise ratio during the playback path of the digital-to-analog converter can reach
up to 100dB

The signal-to-noise ratio is as high as 95dB during the recording path

Capacitor-free stereo headphone driver, 18mW@1.8V

Two stereo differential speaker outputs\

Two low-noise analog microphone offsets