Agilent Technologies J-BERT N4903B, User Manual, Page: 94 / 572

How the Hardware Generates PRBS
2^n -1 PRBS is an inverted, hardware-generated pattern that is created by a series
of shift registers with adjustable feedback. The example below shows the register
configuration for a 2^7 -1 (127-bit) pattern.
The following table describes the operation of XOR'ing two points for the different
patterns.
Table 11
Sequence Length Shift-Register Configuration
2
7
-1 D
7
+ D
6
+ 1 = 0, inverted
2
10
-1 D
10
+ D
7
+ 1 = 0, inverted
2
11
-1 D
11
+ D
9
+ 1 = 0, inverted
2
15
-1 D
15
+ D
14
+ 1 = 0, inverted
2 23 -1 D 23 + D 18 + 1 = 0, inverted
2
23
-1 (2
23
-1p) D
23
+ D
21
+ D
18
+ D
15
+ D
7
+ D
2
+ 1 = 0,
non-inverted
2
31
-1 D
31
+ D
28
+ 1 = 0, inverted
N O T E
2
23
-1p (using D
23
+ D
21
+ D
18
+ D
15
+ D
7
+ D
2
+ 1 = 0) produces the same bit sequence
like the PCIe 3.0 scrambler when fed with zeroes only. The PCIe 3.0 scrambler is
using D
23
+ D
21
+ D
16
+ D
8
+ D
5
+ D
2
+ 1 = 0, with bit numbering being reverse
compared to the N4903B.
3
Setting up Patterns
94 Agilent J-BERT N4903B High-Performance Serial BERT