Agilent Technologies J-BERT N4903B, User Manual, Page: 216 / 572

Starting too late: If the Gate In signal is applied too late, the Bit Count Time will
be shortened, and thus the burst sync ratio will be low (which forces the
measurement of more bursts to obtain the necessary level of reliability).
Data Input
CDR Settling Time
Synchronization Time
Burst
Gate Input
Start too late
Bit Count Time
End
Margin
Ending too soon: If the Gate In is deactivated too soon, the same problems will
occur as with starting the gate too late (see previous point).
Data Input Burst
Gate Input
End too soon
CDR Settling Time
Synchronization Time
Bit Count Time
End
Margin
Ending too late: If the Gate In signal is deactivated too late, the last received bits
will not be part of the burst. Thus, the BER will increase. If the BER is higher than
the Burst Sync Threshold, the burst will be considered a bad burst.
Data Input
Burst
Gate Input
End too late
CDR Settling Time
Synchronization Time
Bit Count Time
Pattern Synchronization - Procedures
To synchronize the incoming pattern to the expected pattern:
1 Press
Pattern Sync
in the
ED Setup
menu.
5
Setting up the Error Detector
216 Agilent J-BERT N4903B High-Performance Serial BERT
Gate In End