Agilent Technologies ESG series, User And Programming Manual, Page: 424 / 446

6-8 Real-Time I/Q Baseband Generator User’s and Programming Guide
Theory of Operation ESG Family Signal Generators
Data Clock Timing Patterns Options UN8 and 202
Data Clock Timing Patterns
The following timing diagram shows the following information:
• external DATA CLOCK INPUT signal in normal and symbol modes
• SYMBOL SYNC INPUT signal in continuous and single modes
• symbol bits (2 bits per symbol)
• DATA INPUT pattern
Notice that the data should change (zero to one or one to zero) on the rising edge of the
data clock and the data must be stable on the falling edge of the data clock.
Ext Data Clock
Data
where X is data transition; = is data valid 0 or 1
=====X========X========X========X========X=======
Normal
Symbol
Symbol Sync
Continuous
Single
Symbol Bit 1 2 1 2