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Chapter 16
W-CDMA Uplink Digital Modulation for Receiver Test
W-CDMA Uplink Concepts
Synchronization Diagrams
Signal Alignment for Default DPCH Mode
illustrates the timing relationships between the signals from the rear panel BNC input and
output connectors relative to the RF Output connector for default signal assignments in DPCH mode. Signal
states are referenced to the chip clock provided at the DATA CLK OUT connector.
Figure 16-78
Signal Alignment for Default DPCH Mode
DPCH Synchronization
illustrates the timing alignment for the DPCH channel. Delay time is defined by the sum of T0
(1024 chips = the standard timing offset between downlink and uplink), timing offset, and timeslot offset.
Summary of Contents for E4428C
Page 22: ...Contents xxii ...
Page 224: ...200 Chapter 4 Basic Digital Operation Creating and Using Bit Files ...
Page 228: ...204 Chapter 5 AWGN Waveform Generator Configuring the AWGN Generator ...
Page 229: ...205 6 Analog Modulation ...
Page 276: ...252 Chapter 7 Digital Signal Interface Module Operating the N5102A Module in Input Mode ...
Page 286: ...262 Chapter 8 Bluetooth Signals Turning On a Bluetooth Signal ...
Page 330: ...306 Chapter 9 BERT Verifying BERT Operation ...
Page 366: ...342 Chapter 10 CDMA Digital Modulation IS 95A Modulation ...
Page 394: ...370 Chapter 12 Multitone Waveform Generator Applying Changes to an Active Multitone Signal ...
Page 468: ...444 Chapter 15 W CDMA Digital Modulation for Component Test W CDMA Frame Structures ...
Page 667: ...643 18 Troubleshooting ...
Page 700: ...Index 676 Index ...