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Chapter 16
W-CDMA Uplink Digital Modulation for Receiver Test
W-CDMA Uplink Concepts
Figure 16-75
Input/Output Signal Alignment
DPCH Mode
provides descriptions for fixed and user-selectable signals available in DPCH mode.
shows an example of DPCH output timing alignment.
Table 16-7
Signal Descriptions for DPCH Mode
Signal Label
Input/
Output
Signal Description
SCPI
Syntax
Frame Sync Trigger
Input
The input signal can be set to either the frame clock
or the system frame number SFN) reset signal by
toggling the
Sync Source FClk SFN
softkey. The frame
clock can be set to 10, 20, 40, 80, or 2560 ms.
FSYN
TPC User File Trigger
Input
Trigger for user-defined TPC bits.
USER
Compressed Mode Start
Trigger
Input
Trigger to start compressed mode.
CSTT
Compressed Mode Stop
Trigger
Input
Trigger to stop compressed mode.
CSPT
None
Output
No signal.
RPS0
Summary of Contents for E4428C
Page 22: ...Contents xxii ...
Page 224: ...200 Chapter 4 Basic Digital Operation Creating and Using Bit Files ...
Page 228: ...204 Chapter 5 AWGN Waveform Generator Configuring the AWGN Generator ...
Page 229: ...205 6 Analog Modulation ...
Page 276: ...252 Chapter 7 Digital Signal Interface Module Operating the N5102A Module in Input Mode ...
Page 286: ...262 Chapter 8 Bluetooth Signals Turning On a Bluetooth Signal ...
Page 330: ...306 Chapter 9 BERT Verifying BERT Operation ...
Page 366: ...342 Chapter 10 CDMA Digital Modulation IS 95A Modulation ...
Page 394: ...370 Chapter 12 Multitone Waveform Generator Applying Changes to an Active Multitone Signal ...
Page 468: ...444 Chapter 15 W CDMA Digital Modulation for Component Test W CDMA Frame Structures ...
Page 667: ...643 18 Troubleshooting ...
Page 700: ...Index 676 Index ...