Agilent Technologies E4428C, User Manual

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Chapter 16 507
W-CDMA Uplink Digital Modulation for Receiver Test
DPCH
symbol rate and slot formats are linked together, a change to one value will automatically adjust the
other when required.
5. Set the bit error rate ratio.
a. Highlight the
TrCH BER Cycle
field.
b. Press
125
>
Enter
.
The value entered composes a group of data bits that can contain a specified number of error bits,
which are entered in the following steps. If you enter zero for the
TrCH BER Cycle
field, this
effectively terminates the error bit insertion feature.
c. Highlight the
TrCH BER ErrLen
field.
d. Press
10
>
Enter
.
This sets the number of error bits contained in the group of data bits shown in the
TrCH BER Cycle
field. The value ten means that ten of the 125-bits are error bits. The error bit
positions are randomly changed to prevent them from appearing in fixed positions and to ensure,
when multiple transport channels are used, that errors can appear across all data blocks. You can also
enter zero for no error bit insertion.
The value for the
TrCH BER ErrLen
cannot be greater than the value for the
TrCH BER Cycle
. If you enter a greater value, the ESG will disregard the entered parameter and set the
field equal to the
TrCH BER Cycle
field setting.
The error ratio is calculated using the following formula:
BER =
TrCH BER ErrLen
/
TrCH BER Cycle
Using the values entered above: BER = 10 / 125
BER = .08 or 8%
The BER is shown in the grayed-out
TrCH BER
field. See Figure 16-40 for the location of the
BER fields.