38
Chapter 2
E4438C Vector Signal Generator Overview
Rear Panel Overview
1. 321.4 IN Connector (Option 300)
Use this female SMB connector to input a downconverted 321.4 MHz GSM/EDGE signal for base
transceiver station (BTS) loopback measurements. (Option 300 also requires Options UN7, 001/601or
002/602, and 402).
2. BER GATE IN Connector (Option UN7)
Use this female SMB connector to input the clock gate signal for the bit-error-rate measurements. The clock
signal to the BER CLK IN connector is valid only when the signal to this connector is a high or low,
depending on your softkey selection or SCPI command. The d
amage levels are > +5.5 volts and <
−0.5
volts
.
This connector accepts a high impedance TTL-compatible signal or a 75
Ω
input. It can be enabled or
disabled by a softkey or a SCPI command.
3. BER CLK IN Connector (Option UN7)
Use this female SMB connector to input the clock signal for the bit-error-rate measurements. The rising
(positive) or falling (negative) edge of the signal (selected either by softkey or SCPI command) causes data
on the BER DATA IN connector to be sampled. The d
amage levels are > +5.5 volts and <
−0.5
volts
. This
connector accepts a high impedance TTL-compatible signal or a 75
Ω
input.
4. BER DATA IN Connector (Option UN7)
Use this female SMB connector to input the data streams for the bit-error-rate measurements. The rising
(positive) or falling (negative) edge of the BER CLK IN signal (selected by the softkey or the SCPI
command) is used to trigger the reading of the data. The d
amage levels are > +5.5 volts and <
−0.5
volts
. This
connector accepts a high impedance TTL-compatible signal or a 75
Ω
input.
5. I-bar OUT Connector (Option 001/601 or 002/602)
This female BNC connector is used in conjunction with the I OUT connector to provide a balanced baseband
stimulus. Balanced signals are signals present in two separate conductors that are symmetrical relative to
ground, and are opposite in polarity (180 degrees out of phase). The nominal output impedance of this
connector is 50
Ω
, DC-coupled. The damage levels are > +2 V and <
−
2 V. The DC origin offset is typically
< 10 mV. The output signal levels into a 50
Ω
load are as follows:
•
0.5 V
pk
, typical, corresponds to one unit length of the I/Q vector.
•
0.69 V
pk
(2.84 dB), typical, maximum crest factor for peaks for
π
/4 DQPSK with alpha = 0.5.
•
0.71 V
pk
(3.08 dB), typical, maximum crest factor for peaks for
π
/4 DQPSK with alpha = 0.35.
•
Typically 1 V
p-p
maximum (Option 001/601or 002/602 only).
Summary of Contents for E4428C
Page 22: ...Contents xxii ...
Page 224: ...200 Chapter 4 Basic Digital Operation Creating and Using Bit Files ...
Page 228: ...204 Chapter 5 AWGN Waveform Generator Configuring the AWGN Generator ...
Page 229: ...205 6 Analog Modulation ...
Page 276: ...252 Chapter 7 Digital Signal Interface Module Operating the N5102A Module in Input Mode ...
Page 286: ...262 Chapter 8 Bluetooth Signals Turning On a Bluetooth Signal ...
Page 330: ...306 Chapter 9 BERT Verifying BERT Operation ...
Page 366: ...342 Chapter 10 CDMA Digital Modulation IS 95A Modulation ...
Page 394: ...370 Chapter 12 Multitone Waveform Generator Applying Changes to an Active Multitone Signal ...
Page 468: ...444 Chapter 15 W CDMA Digital Modulation for Component Test W CDMA Frame Structures ...
Page 667: ...643 18 Troubleshooting ...
Page 700: ...Index 676 Index ...