502
Chapter 16
W-CDMA Uplink Digital Modulation for Receiver Test
Overload Testing with Multiple PRACHs—Multiple ESGs
Figure 16-36
ESG 1 and ESG 2 Frame Timing Setup
ESG 1 is Synchronized
with the BTS Timing
Signal
ESG 1 has Received the
PRACH Start Trigger
(will gray-out when a
trigger is required)
Set to FClk
Set to Cont
ESG 2 is Synchronized
with the ESG 1 Timing
Signal
ESG 2 has Received the
PRACH Start Trigger
(will gray-out when a
trigger is required)
Set to ESG
Set to Cont
ESG 2
ESG 1
Summary of Contents for E4428C
Page 22: ...Contents xxii ...
Page 224: ...200 Chapter 4 Basic Digital Operation Creating and Using Bit Files ...
Page 228: ...204 Chapter 5 AWGN Waveform Generator Configuring the AWGN Generator ...
Page 229: ...205 6 Analog Modulation ...
Page 276: ...252 Chapter 7 Digital Signal Interface Module Operating the N5102A Module in Input Mode ...
Page 286: ...262 Chapter 8 Bluetooth Signals Turning On a Bluetooth Signal ...
Page 330: ...306 Chapter 9 BERT Verifying BERT Operation ...
Page 366: ...342 Chapter 10 CDMA Digital Modulation IS 95A Modulation ...
Page 394: ...370 Chapter 12 Multitone Waveform Generator Applying Changes to an Active Multitone Signal ...
Page 468: ...444 Chapter 15 W CDMA Digital Modulation for Component Test W CDMA Frame Structures ...
Page 667: ...643 18 Troubleshooting ...
Page 700: ...Index 676 Index ...