Chapter 9
291
BERT
Bit Error Rate Tester–Option UN7
Figure 9-21
CH1: BER TEST OUT (pin 20 of AUX I/O connector)
CH2: BER MEAS END (pin 1 of AUX I/O connector)
In this example, the clock delay function is on. The rising edge of the clock was delayed by 200 ns and was
adjusted to the center of the data.
indicates the result of the using the clock delay function.
Figure 9-22
CH1
CH2
CH1
CH2
Summary of Contents for E4428C
Page 22: ...Contents xxii ...
Page 224: ...200 Chapter 4 Basic Digital Operation Creating and Using Bit Files ...
Page 228: ...204 Chapter 5 AWGN Waveform Generator Configuring the AWGN Generator ...
Page 229: ...205 6 Analog Modulation ...
Page 276: ...252 Chapter 7 Digital Signal Interface Module Operating the N5102A Module in Input Mode ...
Page 286: ...262 Chapter 8 Bluetooth Signals Turning On a Bluetooth Signal ...
Page 330: ...306 Chapter 9 BERT Verifying BERT Operation ...
Page 366: ...342 Chapter 10 CDMA Digital Modulation IS 95A Modulation ...
Page 394: ...370 Chapter 12 Multitone Waveform Generator Applying Changes to an Active Multitone Signal ...
Page 468: ...444 Chapter 15 W CDMA Digital Modulation for Component Test W CDMA Frame Structures ...
Page 667: ...643 18 Troubleshooting ...
Page 700: ...Index 676 Index ...