Block Diagram
Block Diagram
The instrument has four main assemblies:
l
Processor
l
Main board
l
Front panel
l
Main power supply
A
appears at the bottom of this section.
The processor is a single board computer that contains the CPU, RAM, ROM, and circuits used to drive the GPIB, LAN,
and USB ports. The built in web interface is contained in the ROM. The processor circuitry is earth referenced.
When the power switch is pressed, the processor communicates with and loads the FPGA. This communication uses
three asynchronous serial data lines and one serial clock line. These four lines are isolated.
The FPGA stores all waveforms except arbitrary waveforms. Arbitrary waveforms are loaded into SDRAM on the main
board. All control of waveforms, triggers, sync signals, output path, attenuation, and offset is provided by the FPGA.
The main waveform for each channel (only one channel is shown in the
) is loaded into the waveform
DAC and clocked by the timebase. The DAC output passes through an elliptical filter before the main attenuators. There
are three attenuators available in the path, -7.96 dB, -15.91 dB, and -23.87 dB.
The signal is applied to the output amplifier. The DC offset is summed at the output amplifier. A post amplifier -23.87 dB
attenuator is available for low level signals. The table below show the attenuators that create the output signal ampli-
tude.
Output Range
DC Offset < 320 mV
-7.96 dB
-15.91 dB
-23.87 dB
-23.87 dB
(post)
10 Vpp - 3.6 Vpp
Out
Out
Out
Out
4 Vpp - 1.44 Vpp
In
Out
Out
Out
1.6 Vpp - 576 mVpp
Out
In
Out
Out
640 mVpp - 230 mVpp
Out
Out
Out
In
256 mVpp - 92 mVpp
In
Out
Out
In
102.4 mVpp - 36.86 mVpp
Out
In
Out
In
40.96 mVpp - 14.75 mVpp
Out
Out
In
In
16.38 mVpp - 5.90 mVpp
In
Out
In
In
6.55 mVpp - 2.36 mVpp
Out
In
In
In
2.62 mVpp - 1.00 mVpp
In
In
In
In
Output Range
DC Offset ≥ 320 mV
-7.96 dB
-15.91 dB
-23.87 dB
-23.87 dB
(post)
9.36 Vpp - 3.6 Vpp
Out
Out
Out
Out
Agilent 33500 Series Operating and Service Guide
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