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2-2 Creating a Test Plan

Test Engineer’s Responsibilities

Agilent 93000 SOC Series User Training Part 1, October 2004

2-2 Creating a Test Plan

Device Information

Gathering information about the device to be tested is an initial step in

the creation of a test plan. Every device will have a data sheet available

that will describe the device in detail; the electrical characteristics,

physical characteristics, environmental characteristics, and so on.

Reading the device data sheet will provide the necessary information

about the device to begin to develop your test plan.

To begin to get an understanding about the device, you should refer to

the data sheet for such information as the function of the device, the

AC and DC characteristics, timing characteristics, the package type

and footprint of the device. All functional pin groups will also be

described in the data sheet.

Shift/Storage Register 74ACT299

General Description

The 74ACT299 is an 8-bit universal shift/storage register cmos device

with tristate outputs. Four modes of operation are possible: hold

(store), shift left, shift right and load data.

The parallel load inputs and flip-flop outputs are multiplexed to reduce

the total number of package pins. Additional outputs are provided for

flip-flops Q0 and Q7 to allow easy serial cascading. An asynchronous

active LOW Master Reset is used to reset the register.

N O T E

To see the complete data sheet for the 74ACT299 shift register, refer to

“Spec Sheet 74ACT299”

on page 553.

Features

• Common parallel I/O for reduced pin count

• Additional serial inputs and outputs for expansion

• Four operating modes: shift left, shift right, load and store

• Tristate outputs for bus-oriented applications

• Outputs source/sink 24 mA

• TTL compatible inputs

Summary of Contents for 93000 SOC Series

Page 1: ...Agilent 93000 SOC Series User Training Part 1 Training Manual S1...

Page 2: ...rnishing use or perfor mance of this document or of any information contained herein Should Agilent and the user have a separate written agreement with war ranty terms covering the material in this do...

Page 3: ...d 29 3 Hardware Overview 33 3 1 Major Components 36 4 Software Overview 51 4 1 SmarTest Test Development 54 4 2 Online Documentation 58 4 3 Running the Software 60 4 4 Start up Screen 62 4 5 SmarTest...

Page 4: ...Test 135 8 Defining the Levels 137 8 1 AC Levels 140 8 2 DPS Device Power Supply Pins 149 8 3 Overview of the Level Setup 152 8 4 Level Setup Steps 158 8 5 Using Formats 168 8 6 Converting Levels 170...

Page 5: ...ubroutines 293 10 10 Vector Generation 296 10 11 Memory Types and Structure 303 10 12 Review Test 307 11 Standard Test Functions 309 11 1 What is a Functional Test 312 11 2 Standard Test Function Grou...

Page 6: ...14 3 Checking for Continuity and Short Circuits 397 14 4 Measuring DC Output Voltages 402 14 5 Measuring Input Leakage 410 14 6 Measuring Operating Current 412 14 7 Related Topics 414 14 8 Summary an...

Page 7: ...asuring Pin Margins 476 17 2 Pin Margin Setup 478 17 3 Summary and Discussion 490 17 4 Review Test 491 18 Advanced Testflow Control 493 18 1 Testflow Variables 496 18 2 Built In Functions 504 18 3 Spe...

Page 8: ...ining Part 1 October 2004 A Appendices 551 B Spec Sheet 74ACT299 553 C UNIX Commands 565 D Linux Commands 573 E Using vi 585 F Pin Margin Algorithm 589 G System File Examples 597 H List of Abbreviatio...

Page 9: ...Agilent 93000 SOC Series User Training Part 1 October 2004 9 1 Training Overview...

Page 10: ...Training Overview 10 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 11: ...ing Part 1 October 2004 11 Training Overview Overview This first lesson gives an overview of the whole training and provides the training agenda What you will learn After this lesson you will be famil...

Page 12: ...tfunctions to test a device evaluate and debug a device using the result analysis and debug tools combine test functions in a testflow to automate the test execution In particular you will be able to...

Page 13: ...Software Overview Lesson 4 Calibration Lesson 5 Lunch Main Test Setup Components Lesson 6 LAB 1 Main Test Setup Components Defining the Pins Lesson 7 LAB 2 Defining the Pins Defining the Levels Lesson...

Page 14: ...our First Testflow Thursday Q and A Test Result Analysis Lesson 13 LAB 9 Debugging Lunch Test Result Analysis Continued Lesson 13 LAB 9 Debugging Continued Device Characterization DC Tests Lesson 14 D...

Page 15: ...1 2 Agenda Training Overview Agilent 93000 SOC Series User Training Part 1 October 2004 15 LAB 14 Histogram Optional...

Page 16: ...Training Overview 1 2 Agenda 16 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 17: ...Agilent 93000 SOC Series User Training Part 1 October 2004 17 2 Test Engineer s Responsibilities...

Page 18: ...Test Engineer s Responsibilities 18 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 19: ...vice used in this training The shift storage register 74ACT299 It provides information on a data sheet level The actual training device used in the online lab exercises is the shift storage register 7...

Page 20: ...undertaken after the decision regarding the ATE platform has been made so the variables such as hardware and software considerations are not a factor in test development The test design criteria will...

Page 21: ...ewly implemented test program Device characterization data collection results analysis and failure analysis are also critical components to the validation and analysis processes Test Enhancement When...

Page 22: ...ill focus on the test plan and DUT board design Figure 1 Flow for setting up a device test DEVICE UNDER TEST DUT Vector Setup Level Setup Calibration Choose or Design a DUT Board Testing the Device Ti...

Page 23: ...ckage type and footprint of the device All functional pin groups will also be described in the data sheet Shift Storage Register 74ACT299 General Description The 74ACT299 is an 8 bit universal shift s...

Page 24: ...2 74ACT299 Shift Register 1 2 3 10 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 Vcc S1 DS7 Q7 I O7 I O5 I O3 I O1 CP DS0 S0 _OE1 _OE2 I O6 I O4 I O2 I O0 Q0 _MR GND 74ACT299 I O0 I O2 I O1 I O7 I O6 DS0...

Page 25: ...tw_CP Clock puls width ts_Sx_CP Setup time of the pins S0 and S1 th_CP_Sx Hold time of the pins S0 and S1 th_CP_Sx tw_MR trec_MR_CP ser_in ts_DSx_CP th_CP_DSx ts_Sx_CP CP tw_CP ts_IOx_CP th_CP_IOx io...

Page 26: ...eristics Vcc levels Input levels VIL and VIH Output levels VOL and VOH Output source sink current IOL and IOH Input and output leakage current limits Supply current Icc AC Characteristics Setup and ho...

Page 27: ...ming as designed An AC test is usually a search type of func tional test where the result is normally a value A DC test is a measure ment of force current measure voltage and vice versa The functional...

Page 28: ...e tests in Testflow order NOTE The vector label names and test names in Table 6 will be explained in later labs Table 6 Possible 74ACT299 Tests in Testflow Order Testsuite Order Functional Tests DC Te...

Page 29: ...nd layout reviews is necessary to prevent overlooked design flaws It is also important to include the DUT board vendor in the design and review of your DUT board to prevent any unnecessary redesign co...

Page 30: ...and Ground 3 Insert the DUT to the tester and check the DPS voltages 4 Place the device and verify the continuity If continuity fails then check the following 1 Check the continuity limits 2 Adjust t...

Page 31: ...tween the I O electronics and the device pins is measured automatically using Time Domain Reflectom etry TDR These values are used to adjust the Per Pin timing so that the differences in wiring length...

Page 32: ...e all major issues when designing a multi site DUT board The component placement area is limited and that in turn limits the number of sites that can be placed on the DUT board The number of sites als...

Page 33: ...Agilent 93000 SOC Series User Training Part 1 October 2004 33 3 Hardware Overview...

Page 34: ...Hardware Overview 34 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 35: ...ts hardware design and orga nization and system capabilities This lesson familiarizes you with the major system components where they are located physically and how they are organized What you will le...

Page 36: ...ies Digital IC Test System with a 1024 Pins Testhead The major components are described in the following sections Digital and Analog Components The channel boards of an SOC testhead reside in cardcage...

Page 37: ...iver receiver active loads relays parametric measurement units PMUs vector memory timing generator and sequencing circuits as well as device power supply modules DPS Load board interface In addition t...

Page 38: ...auxiliary equip ment auxiliary power supply and AC DC converters Rack interface board providing interfaces to all major components of the SOC Series test system Cooling Unit CIF and DIS interfaces Wor...

Page 39: ...its most important components Figure 8 Components of the Manipulator Testhead features supporting Manipulator When mounted to the fork held by the manipulator arms the testhead offers a variety of fea...

Page 40: ...e testhead in Z direction and a 90 degree tilt of the testhead It is suited for clean room applica tions Its zero footprint design allows for the maximum possible wafer prober density saving valuable...

Page 41: ...esthead A programmable logic controller in the cooling unit controls the water flow so that the testhead temperature is kept in a narrow range The cooling unit has two independent water circuits that...

Page 42: ...viding illuminated ON and Standby buttons and an Emergency OFF button Figure 11 ON STANDBY Switches on Support Rack Front Panel The color coded illumination of the push buttons gives basic informa tio...

Page 43: ...lation failure Switching Off the Hardware To switch off the SOC Series test system 1 Press the STANDBY red button on the support rack 2 For maintenance purposes put the line switch at the rear of the...

Page 44: ...Hardware Overview 3 1 Major Components 44 Agilent 93000 SOC Series User Training Part 1 October 2004 Figure 12 Card Cage Locations in Small and Large Testhead Figure 13 512 Pins Testhead...

Page 45: ...oards can only be placed in group 8 System configuration Maximum analog 8 analog modules 384 digital pins Maximum digital no analog modules 512 digital pins The 512 pin DUT board is compatible with a...

Page 46: ...the electronics and relays for 16 tester channels organized in four 4 Channel Modules Each 4 Channel Module provides four independent channels each including the pin electronics for one device pin Be...

Page 47: ...higher throughput The Pin PMU is connected to a DUT pin by closing the corresponding PPMU relay The Pin PMU returns pass fail signals to the test processor where two compare voltage levels received fr...

Page 48: ...he master clock signal is distributed to all cardcages as the timing reference of the system Reference Voltage Generator The voltages generated by the Reference Voltage Generator are used for DC calib...

Page 49: ...on between analog and digital lowest noise and cross talk Enough floor space on the load board for most complex mixed signal applications with external components on the DUT board Optimal layout for m...

Page 50: ...tations have to be taken into account No support of new hardware features like split IO utility lines and new types of power supplies Limited analog accuracy and noise floor specs Only available for t...

Page 51: ...Agilent 93000 SOC Series User Training Part 1 October 2004 51 4 Software Overview...

Page 52: ...Software Overview 52 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 53: ...setup approach It provides an overview of the steps required to develop a device test What you will learn You will learn how the different pieces of the software are related to each other In particula...

Page 54: ...rTest Production Test A production test insures that a device meets its specifications and functions correctly The main goal during production test development is to minimize the production test execu...

Page 55: ...r you can test the device in a furnace at a specific temperature and for a certain period of time and then from these results deduct the life span of the device at room temperature Main Components of...

Page 56: ...ctor and timing data you could also use the vector editor the timing equation editor and the timing spec tool to create the vector and timing setups manually Setup files and Testfunctions The setup fi...

Page 57: ...fication In an equation based setup you use different editors for setup specification and setup verification Let s discuss the tools used in an equation based setup for the level setup The principles...

Page 58: ...can search the full text of the Agilent 93000 SOC Series User Manuals from the first page of the online docu mentation The Online Documentation can be accessed via the SmarTest Report Window as shown...

Page 59: ...he Find button only searches in the first document 4 Enter your search word Search Options Options for Search include Word Stemming finds words that contain part of the search word Sounds Like finds d...

Page 60: ...ies User Training Part 1 October 2004 4 3 Running the Software Selected Files and Directories Structure Figure 20 shows you selected 93000 files and directories that will be useful to you during the c...

Page 61: ...the UNIX command line HPSmarTest options The following options are available NOTE Start the software with the option to display information on further options Invoking the software without selecting...

Page 62: ...l be asked to enter information on a new device or select an existing device Otherwise the software starts up by displaying the Report window the Main Toolbar Operation Control window Figure 21 Start...

Page 63: ...kill_smarTest kill_smarTest is used to get a clean environment if the software has an irregular timeout You find the file kill_smarTest in the following folder opt hp93000 soc prod_env lbin To start t...

Page 64: ...st software is structured in 8 main menus Setup Data Manager Results Debug Memory Test Scan Analog Production System Each main menu has a number of submenus These main menus and submenus are shown in...

Page 65: ...ns corresponding to the submenus listed above When activated the buttons start the software selected and the relevant window is opened The options selected by these buttons can also be selected from t...

Page 66: ...Structure 66 Agilent 93000 SOC Series User Training Part 1 October 2004 Setup Tools Data Manager The Setup tools allow you to set up a test Results Tools The Results tools allow you to view the test...

Page 67: ...000 SOC Series User Training Part 1 October 2004 67 Debug Tools The debug tools are used to activate the debugging aid tools Figure 25 Debug Tools Buttons Memory Test Tools The Memory Test tools activ...

Page 68: ...3000 SOC Series User Training Part 1 October 2004 Scan Test Tools The Scan Test tools activate the device scan test Figure 27 Scan Test Tool Buttons Analog Test Tools The Analog Test tools activate th...

Page 69: ...SOC Series User Training Part 1 October 2004 69 Production Test Tools The Production Test tools activate the production test Figure 29 Production Test Tool Buttons System Tools The System Tools activ...

Page 70: ...ribed below Setup Page You have to create the following setup files to set up a testflow Pin Configuration file Level file Timing file Vector file Pin Attributes file optional The Pin Configuration fi...

Page 71: ...configuration LEVEL Level setup TIMING Timing setup VECTOR Vector setup ATTRIB Pin Attributes setup The files that are currently loaded in hardware are displayed under neath each icon You can load or...

Page 72: ...e training Program Page The program page of the Data Manager allows access to all building blocks of a test program This page is mainly related to a test program needed for production a test program T...

Page 73: ...4 6 The Data Manager Software Overview Agilent 93000 SOC Series User Training Part 1 October 2004 73 Figure 33 Data Manager Menus...

Page 74: ...l sets are downloaded to the hardware If you execute the test you can switch sets from one testsuite to the other Every testsuite points to the sets defined in the setup files see also Testflow Editor...

Page 75: ...ger Program page The Testflow Editor is the top level tool to generate a testflow if all setup files are available The setup files are globally assigned to the testflow For every testsuite you open a...

Page 76: ...ies User Training Part 1 October 2004 The Setup Dialog box where you assign setup files globally to the test flow allows you to access the setup editors associated with the various setup files Figure...

Page 77: ...rs pin_attributes can contain a number of setup files of the respective type For example the timing directory could contain different timing files 74ACT299_tim_relaxed 74ACT299_tim_stressed 74ACT299_t...

Page 78: ...re are communicated to the tester via so called firmware commands For example if you download the Pin Configuration the CONF command is sent to the tester If you change the Level Setup for a pin the D...

Page 79: ...Most of the error messages shown in the Report window also refer to a firmware command When you get such an error message you can look in the Command Reference to read about details of the appropriat...

Page 80: ...What is the command to shut down the SmarTest software if the software has an irregular timeout 3 What is the purpose of the following Data Manager pages a setup b result c program 4 Fill in the blank...

Page 81: ...Agilent 93000 SOC Series User Training Part 1 October 2004 81 5 Calibration...

Page 82: ...Calibration 82 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 83: ...Part 1 October 2004 83 Calibration Overview This lesson describes the steps of the calibration process What you will learn You will learn how the calibration process is structured and what is execute...

Page 84: ...s modules compo nents and interconnections perform according to their specifications at least up to the pogo pins The calibration process compares present values with references and finally yields cor...

Page 85: ...of cali brated modules or boards Once a traceable calibration has been successfully completed the system is guaranteed to meet NIST National Institute of Standards and Traceability and international...

Page 86: ...ation update period for a drive and compare level accuracy of 10mV 2 weeks 15mV 4 weeks 20mV 3 months default To update the DC calibration 1 Start SmarTest See Start SmarTest on page 61 2 In the Main...

Page 87: ...5 2 Calibration Calibration Agilent 93000 SOC Series User Training Part 1 October 2004 87 Figure 38 Starting the DC Calibration Update...

Page 88: ...t be running for at least one hour The system temperature must have stabilized at the programmed value Check this at the temperature meter of the cooling unit The standard diagnostic must have been ru...

Page 89: ...ix NOTE The SOC Series program uses two different types of Calibration matrix The E7008A ICU Integrated Calibration Matrix is required for SOC interface whereas the ACU Automatic Calibration Matrix is...

Page 90: ...ICU Stiffener Figure 41 ICU Connection Cable 3 Click Done in the dialog box to begin the calibration process DC Calibration The Automated Calibration Progress window appears as shown in Figure 42 Firs...

Page 91: ...window or look up the cal_log file located in the directory var opt hp93000 soc calibration for a detailed error information AC Linearity Depending on the pin count for a 256 pin test system approxima...

Page 92: ...ition as indi cated in the dialog window Calibration Procedure see Figure 43 Figure 43 AC Skew Dialog Figure 44 illustrates how you mount the ICU on the ICU stiffener Figure 44 Installing the ICU 2 Co...

Page 93: ...004 93 Figure 45 Connecting the ICU Cable to the Testhead 3 Dock the stiffener The window is updated after a pair of I O channels was calibrated If the calibration of the pair of I O channels was succ...

Page 94: ...values are stored in STD__ as reference for future drive to receive alignment measurements Executing the procedure sends a pulse from the driver to the receiver on a channel with the AC relay open see...

Page 95: ...DR measurement This measurement is required to find out the signal path delays with respect to the pogo pins The AC skew calibration yields signal path delays with respect to a certain point in the IC...

Page 96: ...st calibration data CALDrift D R Alignment results cal_log Error messages generated during calibration process are recorded in this file Auto Calibration Errors If any errors occurred during Auto Cali...

Page 97: ...5 3 Performing the Auto Calibration Calibration Agilent 93000 SOC Series User Training Part 1 October 2004 97 NOTE Before you perform any IC tests any failing PMUs or digital channels must be repaired...

Page 98: ...window The channel attributes page is displayed as shown in Figure 52 Figure 52 Fixture Delay To compensate for the signal path delay on the load board fixture delay you can either load a file contai...

Page 99: ...n you simply load the file of the load board you use for your test select File Load Device Specific Calibration File Structure The fixture delay and pin attributes are stored in the following file str...

Page 100: ...st 1 List the four procedures that make up Auto Calibration a b c d 2 What is the path for the directory that contains system calibration information 3 Which calibration accounts for the signal path d...

Page 101: ...Agilent 93000 SOC Series User Training Part 1 October 2004 101 6 Main Test Setup Components...

Page 102: ...Main Test Setup Components 102 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 103: ...device directory file structure known by the software This lesson covers these functions Basic Test Elements Device Directory Creating a Device Directory Structure of the Device Directory The technol...

Page 104: ...ot let you enter details about your device in any other setup window After deciding how the DUT board wiring allocates the tester channels to the DUT pins you have to enter this information into the s...

Page 105: ...tell the system the voltage and current requirements of the DUT s power pins the off state current definition the setup time the VBUMP voltage Timing There are fourteen Edge Generators for every test...

Page 106: ...on AC or DC After defining the parameters for the device pins levels timing and vectors you have all the necessary information actually test the device The next step is determining what exactly to tes...

Page 107: ...October 2004 107 The Agilent 93000 SOC Series supports 8 drive and 6 receive edge delays per pin In addition it provides one global offset delay for all drive and receive edges This set of 16 delays f...

Page 108: ...ory When your current session is ended the device is saved with the name last used device When you start the system software the system looks for the device_inuse file If it is not in your home direct...

Page 109: ...ilent 93000 SOC Series User Training Part 1 October 2004 109 Figure 56 Create device directory button 3 Enter the device name 4 Click create device Figure 57 Name and save the device directory 5 Click...

Page 110: ...tory When the device directory is created the structure of the directory is defined by the system software to include all the necessary subdirecto ries There is also one hidden file the technology fil...

Page 111: ...input and output signals Default values can of course always be changed from within the appro priate menu screen in the SmarTest software However circumstances may arise where you want to have other...

Page 112: ...h name Path where the device directory is being created Home Dir device name Which device you are editing or using device technology This choice affects among other things the default values for the H...

Page 113: ...onents Agilent 93000 SOC Series User Training Part 1 October 2004 113 Figure 63 Change device window Edit button 3 Enter the new device name then fill out the parameters you want to change from the de...

Page 114: ...5 Press the continue button to finish your device setup Figure 66 Saving user settings for the device directory Figure 67 shows an example of the device directory with user defined parameters Table 65...

Page 115: ...settings dev_tech cmos device_cycles 4096 waveform_sets 32 timing_sets 256 level_sets 32 dps_sets 32 pdc_sets 1 m_sets 1024 routing_sets 256 tester_model act User changed to 4096 dev_tech cmos device...

Page 116: ...Main Test Setup Components 6 2 Device Directory 116 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 117: ...Agilent 93000 SOC Series User Training Part 1 October 2004 117 7 Defining the Pins...

Page 118: ...Defining the Pins 118 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 119: ...in any other setup window This lesson deals with the pin configuration What you will learn In this lesson you will learn how to enter a pin configuration and how to define pin groups to sum up pins wi...

Page 120: ...Pin Name Operating Mode of the Tester Channel STD standard mode is the only option the Type of the Pin This can be input I output O bidirectional IO standard IO pin dc analog pin or DPS DPS connected...

Page 121: ...te menu item always read out the setups stored in the tester itself and store this information to a file Therefore you need to download the pin configu ration successfully no download errors printed t...

Page 122: ...ries User Training Part 1 October 2004 NOTE If you edit the pin configuration and download it you must not save any other setup because these setup data are removed A save would overwrite your setup f...

Page 123: ...the Data Manager setup page Or single click the pin config button in the Main toolbar config page NOTE Much of the information for the pin configuration can be imported from CAE data using translation...

Page 124: ...pass Capacitor DPS pins This entry determines the operating range of the DPS 8 Enter the Tester Channel IO channel syntax The Agilent 93000 test system assigns pins to its channel resources with a 5 d...

Page 125: ...rease the maximum current the numbering of the slave channels has to follow sequentially from the number of the master channel Example DPS11 13 DPS11 is the master channel The channels DPS12 and DPS13...

Page 126: ...Pins 7 3 Entering the Pin Configuration 126 Agilent 93000 SOC Series User Training Part 1 October 2004 Figure 69 Channel Information of the DUT Board Design Guide Figure 70 512 pin Test Head Card Cag...

Page 127: ...ge 1 you need a bypass capacitor of about 100nF to ensure that current swings 60 mA result in voltage ripples below 200mV Current swings 100 mA require a bypass capacitor of about 4 F Performance Rang...

Page 128: ...l wiring of your load board or newer DPS board releases may vary from the values of the table above Specification of the DPS Performance Range As discussed in section DPS Performance Ranges on page 12...

Page 129: ...ult in a number lower than 20000 Pin groups are particularly useful for setups with large numbers of pins It is easier to read the setup displays if fewer pins are displayed grouping pins that belong...

Page 130: ...k copy to copy the selected pins to the list of group members If a group item is selected the pins are inserted above this pin Otherwise they are added to the end of the list NOTE The order of the pin...

Page 131: ...ividual pins already defined pin groups and operators You define the pin group as an expression composed of the pins and pin groups displayed in the Pinlist and Grouplist and the operators add pin pin...

Page 132: ...inlist or a selection of all pin groups to be displayed in the GroupList you can specify a filter in the provided entry field 6 Choose a default operator or 7 Click Copy 8 The selected pins or pin gro...

Page 133: ...Pins Agilent 93000 SOC Series User Training Part 1 October 2004 133 You do not have to follow the sequence of steps described above Instead you can directly enter the group expression choose the compo...

Page 134: ...Defining the Pins 7 4 Defining Pin Groups 134 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 135: ...e c operating mode std fastdiff d type of pin i o io DPS e series resistor in I O channels f bypass capacitor of the DPS channels g tester channel 3 List the two steps you must perform when modifying...

Page 136: ...Defining the Pins 7 5 Review Test 136 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 137: ...Agilent 93000 SOC Series User Training Part 1 October 2004 137 8 Defining the Levels...

Page 138: ...Defining the Levels 138 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 139: ...lesson discusses an equation based level setup It introduces the equation based setup concept which later on also applies to the timing setup What you will learn After this lesson you will be able to...

Page 140: ...and clamps These resources are programmed in the level setup The Agilent 93000 SOC Series provides two different standard channel boards You have to distinguish between the C and P channel boards and...

Page 141: ...P Channel Boards vs Ce Channel Board For the Agilent 93000 SOC Series two different standard channel boards exist These different channel boards are used in the models P330 P600 P800 and P1000 C and...

Page 142: ...the line see Figure 75 Drive Levels For input and input output pins the level setup defines the low vil and high vih voltage levels of input signals Figure 76 Drive Levels Driver Termination The outpu...

Page 143: ...via the internal driver resistance of 50 Termination Voltage For a pure output pin you can program the termination voltage VTerm to an arbitrary voltage level In the case of an io pin the termination...

Page 144: ...terminate Terminating the transmission line solves the above problems With a terminated transmission line the comparator receives a well defined signal from the device output The comparator sees the o...

Page 145: ...This behavior is required to apply a termination voltage to i and io pins Setup Data Required The user specifies the driver s tristate state in the timing setup or in the level setup where the active...

Page 146: ...the case of an edge compare the Edge Generator triggers the Data Sample to sample the compare signal at the point in time specified for the edge compare The Window Formatter is not needed in case of a...

Page 147: ...current is iol IO Pins If you have an io pin you want the active load to control your load currents if the io pin operates as an o pin In order to connect the active load to the io pin the drive must...

Page 148: ...tober 2004 the level setup You have to control the driver in the timing setup that is you have to drive a 1 if you want to terminate with vih and you have to drive a 0 if you want to terminate with vi...

Page 149: ...from constant voltage to constant current Make sure it is high enough to cover functional parts with high current but not so high as to damage improperly socketed devices Figure 80 DPS As already men...

Page 150: ...digital channel If Vbump is not used the first DAC will be active the one with lower address bit coding Each DPS channel is supplied with 2 current DACs one for positive current limit clamp and one fo...

Page 151: ...n application for offcurr min could be if you want to disconnect the DPS to connect another power supply for example a PMU In this case offcurr min would replace a relay on the load board DPS Power Up...

Page 152: ...the level resource Vcc is an equation variable or a spec vari able Equation variables If you use equation variables you have to set up an equation system in the equation editor which determines the va...

Page 153: ...ermine the values of the equation variables The number of equations must equal the number of equation variables The left hand side of an equation is given by an equation variable the right hand side i...

Page 154: ...level file The level file resides in the level sub directory of the device directory The specific values of the level resources are calculated from the infor mation of the EQUATION SETS defined in th...

Page 155: ...ation Editor Figure 84 Level Equation Editor SPEC SETS defined in the Spec Tool Spec Tool Figure 85 Level Spec Tool When you run a test you have to select one level equation set remember you can defin...

Page 156: ...level settings Figure 86 Generation of Level Settings Level Setup Editor You use the Level Setup Editor to verify the resulting level settings Figure 87 shows the Level Setup Editor Figure 87 Level Se...

Page 157: ...of course you have to define more level sets at least two containing different level definitions When you set up a testflow you have to specify a level set for every test element If you want to use d...

Page 158: ...l definitions io level definitions in level sets equations and spec declarations then download Open the Spec Tool 2 Select Select Edit Specifications in the Level Setup Editor Enter spec values for th...

Page 159: ...ariables and equation variables One Spec Set is asso ciated with one Equation Set and one Wavetable A Spec Set links the equation set and wavetable More than one Spec Set may point to the same wavetab...

Page 160: ...n above as a simple template for a fixed level setup That is it does not make use of variables and equations spec parameters Default unit for voltages V The equation set contains the following informa...

Page 161: ...evel voh voh_level PINS io_pins vil vil_level vih vih_level vol vol_level voh voh_level vcl vil_level vch vih_level vcc_level vil_level vih_level vol_level and voh_level are user defined variables You...

Page 162: ...in the equation set The actual values of the spec parameters are specified in the Spec Tool where you define spec sets with the corresponding spec values Download of Equation Sets After you have ente...

Page 163: ...ts even if you do not use specs in the equation set s In order to define a spec set proceed as follows Create new specification 1 In the Level Setup Editor select Select Edit Specifications You see a...

Page 164: ...see a row Specification followed by the equation set number of the associated equation set in this case 1 the spec set number in this case 1 and the spec set description in this case spec_set_1 You ha...

Page 165: ...e Data Manager click Save to update the level file with the new spec set 3 Level Verification After you have set up equation and spec sets and downloaded these sets the system calculates the resulting...

Page 166: ...reen Editing Equation Based Level Values You can overwrite the values resulting from specs and equations in the verification screens Then of course the actual level values differ from the results of t...

Page 167: ...r of the header part indicates that there exist over writes in the level setup If you want to save the overwrites you click SAVE in the Data Manager In order to recover the levels resulting from the e...

Page 168: ...ormat 1 In the Level Setup editor select Format define new format Figure 95 Define Format Window NOTE If no format is defined or if the list holding the displayed pins and groups is empty all existing...

Page 169: ...After the format list is complete enter the format name and press done Other buttons Using the other buttons you can create a format list containing each individual pin set default load an existing fo...

Page 170: ...em to an EBT syntax NOTE This is not a completely automated process The section headers required by the EBT format are not put in as a part of the Generate DPS or Generate Lvl functions 1 In the Level...

Page 171: ...e point of insertion 2 Click Generate Lvl The system combines pins groups that share the same characteristics for example ctrl and ser_in 3 Select either the All Level Sets or One Level Sets radion bu...

Page 172: ...Defining the Levels 8 6 Converting Levels 172 Agilent 93000 SOC Series User Training Part 1 October 2004 Figure 98 Fixed to EBT Level Sets...

Page 173: ...r False It is necessary to create a specification for each equation set using the Spec Tool even if the equation set does not use any spec vari ables 3 In which directory is the level setup informatio...

Page 174: ...Defining the Levels 8 7 Review Test 174 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 175: ...Agilent 93000 SOC Series User Training Part 1 October 2004 175 9 Timing Setup...

Page 176: ...Timing Setup 176 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 177: ...not have a correspondence in the level setup In particular the wavetables are very closely related to the vector setup Therefore this lesson covers the timing and vector setup What you will learn You...

Page 178: ...SOC Series User Training Part 1 October 2004 9 1 Example Timing for the Device 74ACT299 Figure 99 shows the timing actions and the pins of the 74ACT299 test device Refer to Spec Sheet 74ACT299 on pag...

Page 179: ...ds to the wavetable Edge corresponds to the equation set or timing set NOTE Other ATE manufacturers sometimes use different terminology For example the term marker may be used instead of edge and form...

Page 180: ...e Timing and Vector Resources are required to generate a Testflow Figure 101 shows us the structure and the elements of each tester pin Figure 101 Timing and Vector Resources Timing Setup In the timin...

Page 181: ...ster channel the hardware contains a physical waveform table The signals that the tester sends to or receives from the DUT are referenced in the Vector Memory by an index to the physical waveform tabl...

Page 182: ...eform Index and Definition Edge Resources Agilent 93000 SOC testers provide 14 edges per pin Figure 104 shows the available edges and the associated actions Figure 104 Edge Types 14 EDGES per PIN DATA...

Page 183: ...eceive edges used have to occur within a maximum distance of one tester period Drive and receive edges can be programmed independently from each other They can have a distance of more than one period...

Page 184: ...e end of the previous cycle Figure 106 Edge Order Rules A particular physical waveform of a wavetable does not have to use all edges of the global edge set of a wavetable However the global edge set a...

Page 185: ...the physical waveforms Equation and Timing Set 2 Open the Timing Equation Editor Select Edit Equations in the Timing Setup Editor In the Timing Equation Editor create timing equation sets containing p...

Page 186: ...Timing Setup 9 3 Wavetable Setup 186 Agilent 93000 SOC Series User Training Part 1 October 2004 Figure 107 Timing Setup Steps...

Page 187: ...108 Drive Actions Any drive edge d1 d8 can switch the drive state Drive voltages It can switch the driver to one of the following drive voltages 1 drive high vih 0 drive low vil N or it does not swit...

Page 188: ...es occur delayed to the point in time defined by the drive edge position Waveform example The physical waveform shown below is one of the 32 possible wave forms which are stored in the physical wavefo...

Page 189: ...tain point in time This point in time is called an edge A sequence of edges together with the associated actions defines a waveform Depending on the actions which can occur at an edge we have drive ed...

Page 190: ...ng a certain time interval Table 112 lists the window compare actions Table 111 Edge Compare Actions List of Edge Compare Actions L compare to low H compare to high M compare to intermediate X don t c...

Page 191: ...of essential impor tance for the vector setup You define the physical waveforms according to the scheme illustrated in Figure 113 Figure 113 Physical Waveform Table Every entry of the Physical Wavefor...

Page 192: ...ak waveform That is the physical waveform indices cover the range 00 1f hex representation of physical waveform indices Wavetables Physical waveforms are defined in wavetables Figure 114 explains the...

Page 193: ...must be of length one and it must be defined for all pins and pin groups If possible one of the existing device cycles should be used in order to save tester resources PINS The key word PINS introduc...

Page 194: ...vetables establish the relations between physical waveform indices stored in the vector memory and physical waveforms stored in the physical waveform table Figure 115 Figure 116 and Figure 117 show th...

Page 195: ...in the Vector Setup Editor you do not see hex numbers because the Vector Editor only displays device cycle names The default device cycle names displayed in the Vector Setup Editor are decimal numbers...

Page 196: ...1 October 2004 When to Use Different Edges to Define Pins Figure 118 and Figure 119 shows when it is necessary to use different edges and when to use the same edges when defining pins Figure 118 Defin...

Page 197: ...R Or press Return to display the wavetables 5 Enter the wavetable name WAVETBL gross_func_wtb 6 Define the display mode as DISPLAY multi 7 Enter the default device cycle DCDT 8 Define the physical wav...

Page 198: ...DNRZ signals only this wavetable gets used for relaxed functional verification DISPLAY multi DCDT Phy Waveform Edge Indices Actions PINS CP 0 d1 0 d2 0 1 d1 1 d2 0 f brk PINS _MR 0 d1 0 d2 1 1 d1 1 d2...

Page 199: ...veform table The device cycle names are used to describe the edge actions Figure 120 shows the wavetable structure including device cycle names for the wavetable gross_func_devcyc_wtb Figure 120 Wavet...

Page 200: ...then enter the Device Cycle names Download and save 5 After all inputs have been made click Download 6 Single click the Timing symbol in the Data Manager and click save Example wavetable In a wavetabl...

Page 201: ...ing Setup Agilent 93000 SOC Series User Training Part 1 October 2004 201 1 d1 1 1 brk PINS io_pins 0 d1 F00 r1 X 0 1 d1 F10 r1 X 1 2 d1 F0Z r1 L L 3 d1 F0Z r1 H H 4 d1 F0Z r1 X X brk PINS ser_out 0 r1...

Page 202: ...he wavetables Timing Set The timing set is defined in the equation set The timing set is needed to define the values of the edges Figure 121 illustrates the assignment of wavetables to timing equation...

Page 203: ...ng Sets Timing Setup Agilent 93000 SOC Series User Training Part 1 October 2004 203 Figure 122 Edge Delays Figure 123 explains the used syntax to create an Equation Set with fixed values Figure 123 Eq...

Page 204: ...ne the timing set numbers and names TIMINGSET 1 20 MHz TIMINGSET 2 50 MHz Enter period and edge delays 7 Define the period 8 Define the edge delays for every pin used Download and save 9 When you have...

Page 205: ...Part 1 October 2004 205 PINS CP d1 20 d2 45 PINS mode ser_in d1 0 d2 30 PINS _MR d1 0 d2 15 PINS ser_out r1 45 PINS io_pins d1 2 r1 45 TIMINGSET 2 50MHz period and edge delays for a 50MHz test period...

Page 206: ...Timing Setup 9 4 Equation Sets and Timing Sets 206 Agilent 93000 SOC Series User Training Part 1 October 2004 PINS ser_out r1 21 5 PINS io_pins d1 1 r1 7...

Page 207: ...iming equation set The spec set points to the wavetable you want to assign to the timing equation set You define spec sets for two purposes In general you use specs in your equation sets But in the eq...

Page 208: ...nge Create Specification You see the Select timing equation set window 6 Select the equation set you need and press create You see the Create timing spec set window 7 Select the Spec Set number you ne...

Page 209: ...th the same equation set and another Spec Set number Figure 126 shows you the SpecTool window and the explanations of the window Figure 126 Specification 2 NOTE To change the values of the edges and p...

Page 210: ...efine the period and use Spec variables for edge delays Assign values to Spec variables Points to a Wavetable Declare a different set of variables Wavetable a Wavetable b Wavetable c Equation Set 1 Ti...

Page 211: ...ription Since edge delays are pin resources it is necessary to select a pin or pin group to view the actual edge placements Once you have selected a pin or pin group by clicking on it you can switch b...

Page 212: ...9 6 Timing Verification 212 Agilent 93000 SOC Series User Training Part 1 October 2004 Timing Setup Editor You use the Timing Setup Editor Figure 128 to verify the resulting timing Figure 128 Timing...

Page 213: ...illustrates the period verification screen Figure 129 Period Verification You can overwrite the period value in this screen Verification Option Edge Delay To display the actual delay values for a part...

Page 214: ...214 Agilent 93000 SOC Series User Training Part 1 October 2004 Figure 130 Edge Delay Verification Modify edge delay You can modify the edge delays by overwriting the delay values displayed in the row...

Page 215: ...ect Marker Figure 131 illustrates the marker screen Figure 131 Measuring Edge Delays Highlight the corresponding pin or pin group in the column Pin Group for which you want to measure edge delays Move...

Page 216: ...Series User Training Part 1 October 2004 Verification Option Description To display the descriptions of the equation set spec set timing set and wavetable choose Select Description Figure 132 illustr...

Page 217: ...ee the select device cycle name window from which you can select a device cycle name or a physical waveform index This depends on the definitions made in the wavet able You select a device cycle name...

Page 218: ...the pins and groups will be displayed To allocate individual device cycle names to each pin you have to set up a format described as follows Open Define format window 1 In the Timing Setup Editor sele...

Page 219: ...9 7 Display Signals and Using Formats Timing Setup Agilent 93000 SOC Series User Training Part 1 October 2004 219 Figure 134 Setup the Format 1 Figure 135 Setup the Format 2...

Page 220: ...s which let you specify the shape and data separately on every vector Comparison of Physical and Logical Wave forms Figure 136 shows a comparison of physical and logical waveforms Figure 136 Compariso...

Page 221: ...9 8 Logical Waveforms Timing Setup Agilent 93000 SOC Series User Training Part 1 October 2004 221 Figure 137 Relation between Logical and Physical Waveforms...

Page 222: ...93000 SOC Series User Training Part 1 October 2004 Logical Waveforms Definition of logical waveforms Figure 138 summarizes the definition of logical waveforms as described below Figure 138 Wavetable s...

Page 223: ...ical waveforms associated with a logical waveform are derived from the logical waveform by replacing the data parameters of the logical waveform by specific actions Device cycles using the command DCD...

Page 224: ...c searches DISPLAY multi DCDT df PINS CP WFDS 0 d1 D11 d2 0 0 0 1 1 BWDS DCDF R0 0 DCDF df 0 PINS _MR WFDS 0 d1 D11 d2 1 0 0 1 1 BWDS d1 F10 DCDF R1 0 DCDF df 0 PINS mode WFDS 0 d1 C11 d2 D11 d3 C11 0...

Page 225: ...df 0 PINS io_pins WFDS 0 d1 C11 d2 D11 d3 C11 0 0 1 1 WFDS 1 d1 F10 r1 EE1 2 L 3 H 4 X DCDF SBC 0 DCDF EDGE 1 DCDF df 0 Overview of Data Parameters If you define logical waveforms you have to enter d...

Page 226: ...data parame ters of Table 141 on page 226 Table 141 Logical Waveform Drive Data Parameters List of Logical Waveform Drive Data Parameters D1N Drive parameter 1 tristate hold D2N Drive parameter 2 tri...

Page 227: ...e Actions on page 190 Table 142 Drive Data Parameters and Associated Fixed Actions Drive Parameter Logical Waveform Drive Fixed Actions Physical Waveform D1N D2N C1N C2N F0N F1N DN1 DN2 FN0 or Z FNZ o...

Page 228: ...Device_Cycle_Name 1 2 3 1d 1e 1f Note that the individual logical waveform indices are separated by a space The maximum length of a device cycle is 16 Later on in the pattern the pair of device cycle...

Page 229: ...ries User Training Part 1 October 2004 229 Figure 145 Logical Wavetable Syntax mode Example 2 The tester considers both wavetables equal since they describe iden tical physical waveform actions Figure...

Page 230: ...orms Classic Single Multi The display modes do not add anything new to what you have learned so far about waveform definition Rather the display modes provide different options to display patterns dep...

Page 231: ...e 148 Vectors Displayed in Classic Mode The classic mode has no device cycle columns Since the wavetable only defines a single device cycle a device cycle column is not necessary Single Mode The singl...

Page 232: ...nt 93000 SOC Series User Training Part 1 October 2004 Figure 149 Wavetable Using Single Mode The wavetable gross_func_wtb single defines the device cycles std and reset for every pin Figure 150 shows...

Page 233: ...in classic mode have only defined one device cycle and every vector necessarily must use this device cycle Patterns displayed in single mode can have defined a number of device cycles and every vector...

Page 234: ...Timing Setup 9 8 Logical Waveforms 234 Agilent 93000 SOC Series User Training Part 1 October 2004 Figure 151 Wavetable Using Multi Mode Figure 152 shows a pattern displayed with the wavetable above...

Page 235: ...2 Vectors Displayed in Multi Mode In multi mode every pin or pin group is associated with a DEVCYC column in the Vector Setup Editor The pattern of Figure 152 shows data parameters for the pins io_pin...

Page 236: ...MING icon in the Data Manager or press the Timing button from the main menu pushbuttons 2 Select Select edit waveforms timing Figure 153 The Timing Setup Window Timing Setup Window The Timing Setup wi...

Page 237: ...ster cycles and to assign shapes to edges to create waveforms The Timing Entry Area Display Options Display Options or so called Overlays Figure 154 The Timing Entry Area Display Options NOTE The othe...

Page 238: ...Cursor and Marker Option The Cursor and Marker Option provides a cursor for absolute and relative timing settings a marker for absolute and relative timing settings Description Option The Description...

Page 239: ...o define a device cycle The device cycle will be defined for one or more pins The device cycle name can describe the actions which take place at one or more pins 1 Select DevCycEdit Define 2 Click the...

Page 240: ...rd step when setting up the timing is to assign shapes to the edges to create waveforms 11 Select the edges to which you wish to assign a shape one two or three edges depending on the shape Use click...

Page 241: ...ou wish to assign Use the Select menu in the Shapes window to toggle between both pages Defining the Break Waveform When the test system is in the break state the break waveform is issued A break wave...

Page 242: ...2 Select Select device cycle 3 In the dialog box select the BREAK device cycle Figure 158 Defining the Break Waveform For pins without a drive component you see BREAK indicating that the BREAK device...

Page 243: ...window If you need more than 16 waveforms you should ensure that these settings allow 32 device cycles wavetable To edit the device settings 1 In the main menu bar select Actions Change Device You se...

Page 244: ...ould be device cycles 512 waveform sets 16 This results in a maximum of 32 device cycles per wavetable Other combinations are possible with the general limits device cycles 2048 waveform sets 64 For e...

Page 245: ...ed is only a fraction of the ASCII vectors depending on the x mode factor When you use Xmodes for higher data rates you automatically get vector compression as well Pin cards may have 7 14 28 56 or 11...

Page 246: ...d X5 are somewhat problematic because you run out of physical waveform indices For example 34 81 physical waveform indices for output pins L H X at X4 35 243 physical waveform indices for output pins...

Page 247: ...9 10 X modes Timing Setup Agilent 93000 SOC Series User Training Part 1 October 2004 247...

Page 248: ...Timing Setup 9 10 X modes 248 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 249: ...ming set defined 3 True or False The physical waveform table specifies the edge actions and edge delays 4 Fill in the blanks The 93000 test system provides _____ edges per pin which includes _____ dri...

Page 250: ...0 What is an alternative way to represent that action 8 Do the order of the receive edges in a wavetable matter Explain 9 True or False All drive edges used have to occur within a maximum distance of...

Page 251: ...ing spec variables in the SPECS module 14 Explain the statement The SPEC variables are used externally 15 Explain the statement The EQN variables are used internally 16 Given the following portion of...

Page 252: ...2004 b What are the physical waveform indices c What are the device cycle names 17 What do the following drive parameters mean What are their corre sponding drive fixed actions for physical waveforms...

Page 253: ...Agilent 93000 SOC Series User Training Part 1 October 2004 253 10 Vector and Pattern Management...

Page 254: ...Vector and Pattern Management 254 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 255: ...ng huge amounts of vector data This lesson also discusses how you debug and edit the resulting vector file in the Vector Editor You can change Timing and Level Sets during a single test by means of se...

Page 256: ...Editor does not display these pointers directly It displays device cycles names according to the device cycle names defined in the wavetable you use for the vector setup Select wavetable In order to d...

Page 257: ...bel Labels are stored in vector files A vector file can contain a number of labels Figure 162 Labels in Vector Files The ASCII Interface can generate a vector file which contains all labels you need f...

Page 258: ...bit would require a download of the whole file Working with large vector files this can be a very time consuming procedure It would be much better if individual labels could be stored in individual f...

Page 259: ...ction Timing Setup Based on Logical Waveforms and Data Parameters on page 310 In this case the physical waveform indices in the vector memory are represented by device cycle names and additional value...

Page 260: ...e edit field for example physical 2 Select a pin or a pin group from the list boxes labeled pinlist and grouplist 3 Define the columns in the vector table for the selected pin or pin group and mark th...

Page 261: ...lumn Sequencer Instructions are entered in the Instr column see Sequencer Instructions on page 246 The width of the Instr column can be customized in the entry field Instr Width The column width is sp...

Page 262: ...2004 Figure 165 Loading a Label Figure 166 shows a label using the wavetable gross_func__devcyc_wtb Figure 166 Vector Setup Composed of Device Cycle Names and Data Parameters Defining Labels Defining...

Page 263: ...efinition 2 Enter a label name in the entry field Test Label 3 Mark the check box Wave Table 4 Click into the entry field Wave Table You see a menu of the wavetables defined in timing setup 5 Select a...

Page 264: ...ect a Label You see the Select Test window Select wavetable 2 In the Select Test window click in the Wave Table edit field and select a wavetable from the dropdown menu see Figure 168 3 Click Select F...

Page 265: ...anagement on page 272 So from time to time there is a need to save a single label from a vector file with a number of labels in its own file You do this using the Save Partial option as defined below...

Page 266: ...cal waveform indices displayed in the Vector Setup Editor Figure 170 shows this vector setup Figure 170 Vector Setup Using Default Device Cycle Names Using User Defined Device Cycle Names In the timin...

Page 267: ...ble does not define a waveform for a phys ical waveform index stored in the vector memory you see a question mark in the Vector Setup Editor for this unresolved pointer Figure 172 shows an example wit...

Page 268: ...ce cycle names The procedure below shows how you can debug device cycle names name which cannot be interpreted These are shown as question marks in the Vector Setup Editor Change Wave table 1 Select S...

Page 269: ...ctober 2004 269 Figure 173 Wavetable PhysIndices 3 Press Select New Device Cycle Names The Device Cycle Names now appear in the Vector Setup Editor as shown in Figure 174 on page 270 The question mark...

Page 270: ...umbers and the device cycle names expressed in the standard hex representation see Figure 173 on page 269 BURST Mode You can combine different labels to one burst label Burst labels allow you to creat...

Page 271: ...labels to the testsuites in the testflow entry field Vector Label in the testsuite window If you have defined a burst you can enter the burst name in the field Vector Label of the testsuite window The...

Page 272: ...ility to arrange the vector files in the file system As in a basic scenario the individual tests of the testflow point to vector labels However in a general scenario the list of vector labels is not s...

Page 273: ...ster file is an ASCII file It specifies the vector files and the corresponding paths As already pointed out vector files are normally generated automati cally using the ASCII Interface The ASCII Inter...

Page 274: ...his case you include more than one path files blocks in the pattern master file hp93000 pattern_master_file 0 1 path path1 files file11 file12 file13 path path2 files file21 file22 file23 Loading a Pa...

Page 275: ...from the Files list 4 Click Load Pattern Manager After loading a pattern master file you can access the individual labels edit them load and save vector files from the Pattern Manager To open the Patt...

Page 276: ...list The associated vector is automatically highlighted Saving Labels To save the changes you have made to a particular vector label to the associated vector file proceed as follows 1 Select the labe...

Page 277: ...have downloaded a huge amount of vectors residing in different files It would consume a lot of time in a debugging cycle if you always had to download the complete set of vectors after every change in...

Page 278: ...dices device cycle data parameters Debug wavetable In a debugging scenario you might want to directly view the physical waveform indices in the vector memory For this purpose you define a debug waveta...

Page 279: ...t corner of the Vector Setup window You can directly type in the pin or pin group name into the entry field Alternatively you can select the pin or pin group from a selection box You do this as follow...

Page 280: ...default device cycle in a wavetable If the default device cycle or the device cycle you have explicitly entered is associated with data parameters the system automatically enters default values for t...

Page 281: ...alues for the data parameters A 0 for every input pin or the drive part of an IO pin An X for every output pin or the receive part of an IO pin Inserting Vectors You can insert a range of vectors at a...

Page 282: ...ith data parameters specify the data parame ters If the default device cycle or the device cycle you have explicitly entered is associated with data parameters the system automatically enters default...

Page 283: ...ors Copy and Paste of Vectors You can copy and paste vectors of your vector setup You specify a range of vectors which you want to paste somewhere else in your vector flow The range of copied vectors...

Page 284: ...n also specify a repeat factor 5 In start vector specify the position in your vector flow where you want to insert the copied vectors or the beginning of the vector range you want to overwrite If you...

Page 285: ...ave a column empty the vector which is to be replaced by the vector of the replace line will keep its entries at this position Start search 4 Position the cursor in the pattern at the vector after whi...

Page 286: ...tches The system replaces all matches with the vector defined in the replace line To replace all vectors in a certain vector range 1 Select VecEdit replace matches in range You see a dialog box headed...

Page 287: ...4 287 NOTE 5 This option is different from using VecEdit replace all remaining matches If you use this option vector 0 cannot be included in the search because you have to position the cursor in vecto...

Page 288: ...ilable see Table 2 You can include comments in the sequencer instruction column To do this just enter a in front of the comment text You can enter more than one instruction per line To do this separat...

Page 289: ...ith the settings of the new timing set specified by the CTIM command NOTE To return to the primary set as defined in the Data Manager you can program CTIM prm Changing the Level Set CLEV To change the...

Page 290: ...93000 SOC Series User Training Part 1 October 2004 CAUTION The reprogramming of the system takes time So the system has to send break waveforms to the DUT Make sure you have set the BREAK waveform in...

Page 291: ...o the DUT using only a few vectors This can be used for example to produce a warm up routine repeating a block of vectors hundreds or thousands of times just to get the DUT up to operating temperature...

Page 292: ...t vector you want to be in the match loop and MATCHEND one vector after the last vector you want to have in the match loop If no match is found the system repeats the vectors until the time out is rea...

Page 293: ...s are available NOTE Jumps and subroutine calls require no break waveforms How to Define a Subroutine 1 In the Vector Setup window select Select select a label You see the Select Test dialog box This...

Page 294: ...to be converted from label type MAIN to label type SVEC and vice versa You can only convert a subroutine to a main label if it is not called in one of the main labels How to Insert a Subroutine Call...

Page 295: ...e repeat factor edit field enter how often the call is to be executed 5 Click Insert The name of the subroutine and the repeat factor are displayed in the Instr column of the Vector Setup Editor NOTE...

Page 296: ...re shows the operation mode of the ASCII interface in broad outline Figure 189 Input and Output of ASCII Interface ASCII Device Cycles The input information is organized by so called ASCII device cycl...

Page 297: ...rmines the time frame of the actions associated with one state character this value will be referred to as an ASCII period The following figure shows an example block from an ASCII timing file Figure...

Page 298: ...ften it is to be sent to the DUT in the format Rx and the name of the ASCII device cycle according to which the state characters are to be interpreted In the example all three ASCII vectors have the s...

Page 299: ...lated into 4 waveforms with the physical waveform indices 0 through 3 In this example the waveforms are coded in the pure physical wave form format The first column contains the physical waveform inde...

Page 300: ...characters Using this file the vector translator determines the correct index for any state character in the ASCII vector file by the column to which the character belongs identifying the pin and by t...

Page 301: ...a of pin Q0 at the address 0 The smallest unit of the Vector Memory that can be accessed for load operations is 28 bytes Only the first 7 bytes of the binary data are displayed in Figure 194 The first...

Page 302: ...Vector and Pattern Management 10 10 Vector Generation 302 Agilent 93000 SOC Series User Training Part 1 October 2004 Figure 195 Basic Translation Process of the ASCII Interface...

Page 303: ...he 93000 per pin architecture is defined by each pin having its own Vector Memory VM This is the 93000 tester per pin concept Available Memory Module options per pin 7 MV x 6 Bits 14 MV x 6 Bits 28 MV...

Page 304: ...t word 8 9 10 11 12 13 14 checksum 8 9 10 11 12 13 14 checksum 15 16 17 18 19 20 21 checksum 15 16 17 18 19 20 21 checksum 22 23 24 25 26 27 28 checksum 22 23 24 25 26 27 28 checksum 6 Bits 6 Bits 6 B...

Page 305: ...ent 93000 SOC Series User Training Part 1 October 2004 305 The checksum bits are only used internally by the tester hardware for error correction therefore the user does not have to be concerned about...

Page 306: ...Vector and Pattern Management 10 11 Memory Types and Structure 306 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 307: ...f defining a format in the vector setup editor 3 Describe how to load a label in the vector setup editor 4 Explain why you might see question marks in the vector setup editor and what you could do to...

Page 308: ...n with the appropriate action 9 True or False Defining subroutines can save vector memory if you have to call the same vector sequence several times in your pattern CTIM repeat until no errors CLEV re...

Page 309: ...Agilent 93000 SOC Series User Training Part 1 October 2004 309 11 Standard Test Functions...

Page 310: ...Standard Test Functions 310 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 311: ...the user interface or they may be run under the control of test flow programs What you will learn This lesson describes what the test function is the user interface asso ciated with the standard test...

Page 312: ...tailed Error Memory per pin Also a pass fail flag per pin is created NOTE The two error memories can be observed with the result analysis tools Error Map Timing Diagram Softscope and State List The te...

Page 313: ...t flag to determine whether it is already connected to the DUT If it is not the Connect function is called which performs the following connect sequence The sequencer is set to OFF state if it is not...

Page 314: ...nect testfunctions at the beginning of any testfunction if not already connected at the beginning of a testflow at the end of a testflow when one of the items of the State menu in the Test Control win...

Page 315: ...for each 4K block of cycles The Overview Error Map can be used to position the detailed error memory Detailed Error Memory Detailed Error Memory The detailed error memory can hold pass fail informatio...

Page 316: ...the Test Control window as shown in Figure 202 Figure 202 Groups of Test Functions As shown in Figure 202 the following groups are available Mixed Signal Tests DC Tests AC Tests Sweep Tests Other Test...

Page 317: ...atus dps_status provides status information about dps pins general_pmu general_pmu allows direct control of the Parametric Measurement Unit PMU in order to force a voltage and measure current or force...

Page 318: ...data This test function provides result data for the Error Map State List and Timing Diagram Windows global_search global_search performs a linear one dimensional sweep of an arbitrary parameter in o...

Page 319: ...re tracked with the spec parameters This test function requires an equation based test setup Other Tests Descriptions of some of the tests that might be found in the Other Tests group are listed below...

Page 320: ...rol start_sequencer start_sequencer starts the vector sequencer and lets you stop it by break test_state test_state gets the present state of the tester running off or break and the status of the PASS...

Page 321: ...her tests return only pass fail informa tion or measure a value and whether tests are performed on individual pins or on all pins at the same time The Test Mode also determines if a test is run in cyc...

Page 322: ...ntrol is passed back to the user This is done in order to make sure all relays are in a known state In the case of the Continuity test function Connect is executed first followed by Disconnect NOTE Ex...

Page 323: ...r Both methods detect open circuits and short circuits between the measured pin and ground However only a test using the program mable load can detect shortcircuits between pins Also for large numbers...

Page 324: ...e executed in the optimized mode This applies for continuity tests using the PPMU as well as for conti nuity tests using the programmable load Each device pin will have ESD Protection diode s and one...

Page 325: ...ch as input clamp diodes by forcing a current into a device pin and measuring the voltage between that pin and ground check for short circuits Figure 206 Continuity Test Using the PPMU Connecting the...

Page 326: ...volt min measured voltage pass volt max When there is an internal DUT connection between the DUT pin and ground the voltage detected is the forward bias voltage of the internal device protection diod...

Page 327: ...in This current should be large enough to be measured but not so large as to damage the diode paths being checked If you select the single radio button to check a single polarity only then the current...

Page 328: ...s test is used to check the chip bonding and connections to the test fixture check protection circuits in the DUT such as input clamp diodes by forcing a current into a device pin and measuring the vo...

Page 329: ...previous 3 cycles The comparator measures the voltage The high and low levels of the comparator are set to the pass volt max and the pass volt min respectively A compare to intermediate state is exec...

Page 330: ...1V above or below Vpass_max as shown in Figure 209 and has a range of 2V to 6V In Figure 209 the polarity of the commutation voltage is set by the polarity of the test current If you ve set the both...

Page 331: ...gative For both polarities the maximum value is 2V These maximum values ensure that the commutation voltage for the programmable load remains within specifications The minimum swing between pass volt...

Page 332: ...opy C paste P Step 2 Select the Edit Menu and Select defaults Menu Step 5 Click the new Button Step 4 Select continuity Test Step 3 Select the DC Tests Step 1 Double Click the Icon Edit defaults copy...

Page 333: ...two diodes like the example on the slide then you can also perform the positive and negative polarity tests a Force positive current 100 uA to 200 uA to forward bias the diode that is connected to VD...

Page 334: ...iscon nected then the CONNECT test function is executed If it is already connected then the functional test continues Further details about the use of the CONNECT test function and associated informat...

Page 335: ...This cannot be achieved if the sequencer is running in an endless loop If you do need to run the sequencer in endless loops for instance in order to stimulate the DUT with drive data while evaluating...

Page 336: ...er 2004 The Functional Test Window will be displayed as shown below Figure 214 Functional Test Window Select any Test Options required and then If not already done enter the sequencer start label in t...

Page 337: ...1 October 2004 337 11 6 Review Test 1 Name one test function from the Other Tests group and describe what it is for 2 Name one test function from the Sequencer Control group and describe what it is f...

Page 338: ...Standard Test Functions 11 6 Review Test 338 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 339: ...Agilent 93000 SOC Series User Training Part 1 October 2004 339 12 Putting It All Together...

Page 340: ...Putting It All Together 340 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 341: ...evice The actual test is set up in the Testflow Editor Here you combine the various setup modules in test elements to complete setups This lesson introduces the testflow on a level where you can set u...

Page 342: ...ructure A testflow is a sequence of individual testsuites These testsuites can be connected in a multitude of different ways sequentially dependent on previous results while a condition is valid and s...

Page 343: ...the testflow and its testsuites as follows The setup files are globally assigned to the testflow That is these files are stored in the tester hardware You cannot and nobody would do this reload setup...

Page 344: ...he information about a complete setup of sets label and testfunction which then is assigned to the testsuite This approach is called a data set based testflow The standard approach is the testfunction...

Page 345: ...alog 1 Either In the Testflow Editor select Select setup or press the pushbutton in the tool bar of the Testflow Editor You see the global setup dialog box Figure 217 Global Setup Dialog Box Enter req...

Page 346: ...where you make a selection Saving the Testflow in the Device Directory When you setup a testflow so far you have assigned global setup files to a testsuite it is not automatically downloaded to the te...

Page 347: ...isplays a list with the available testflows 4 Select a testflow and click Load These steps copy the testflow file from the device directory to the temporary file var opt hp93000 soc hp83AAAa number Te...

Page 348: ...e automatically when you create a testflow To download a setup file from the setup dialog box 1 In the Testflow Editor select Select Setup You see the Setup Dialog window 2 In the Setup Dialog window...

Page 349: ...download the Pin Configuration first The Timing setup must be loaded before the Vector setup Editing Setup Files To edit existing setups from the setup dialog or to create new setups from the setup d...

Page 350: ...Putting It All Together 12 2 Assigning the Global Setup Files 350 Agilent 93000 SOC Series User Training Part 1 October 2004 Figure 221 Editing Setup Files...

Page 351: ...estsuite in the testflow as follows Insert testsuite 1 Select the required insertion point in the testflow 2 In the Testflow Editor select Insert run test or Insert run and branch The appropriate Test...

Page 352: ...ppears empty and you have to enter the set number manually You see the dialog box Select Timing Equations Timing Specs Select a combination of timing equation set and spec set from the selection box S...

Page 353: ...testfunc tions with special settings Then this name identifies the testfunc tion and is displayed in a selection box when you define new testsuites 7 Click Done in the Testsuite Editor Downloading Se...

Page 354: ...current name is not the right one select the name of the setup file or enter a new name 3 Click the Edit button If necessary the selected file is downloaded to the tester and you see the appropriate...

Page 355: ...figure above Hold Flag Hold Independent of the test result test execution stops after that testsuite Hold on Fail Flag Hold on Fail Test execution stops after that testsuite if the testsuite fails If...

Page 356: ...ee the Testflow Flags window Figure 226 Testflow Flags Dialog The global flags hold_on_fail and global_hold correspond to the testsuite flags hold on fail and hold respectively Here we only want to me...

Page 357: ...evices end up that have failed a test It shows up as an octagon stop sign good bin In a Good Bin devices end up that pass the test It shows up as a triangle To insert a new bin into the flow Insert bi...

Page 358: ...Enter the Color in which the bin shows up in the testflow and also in the results display and real time wafermap 7 Select whether reprobe actions should be performed prior to binning the device Reprob...

Page 359: ...execution select File abort At the beginning of the testflow the connect sequence is performed at the end of the testflow the disconnect sequence The Test Result Display window appears on the screen...

Page 360: ...er way of partially executing a testflow is provided by the Exec All Stop Here button in the Testsuite Dialog window This executes the testflow from the beginning and stops after the testsuite which i...

Page 361: ...om the Testflow Editor To save your setup from the Testflow Editor 1 Select File save setups 2 The software automatically checks the setups If there are any changes the following dialog window appears...

Page 362: ...Putting It All Together 12 6 Saving Setup Files 362 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 363: ...st 1 What is a functional test 2 Explain the statement The tester is in the DISCONNECTED state 3 List the actions that occur during the tester s connect sequence 4 What are the two types of error memo...

Page 364: ...Putting It All Together 12 7 Review Test 364 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 365: ...Agilent 93000 SOC Series User Training Part 1 October 2004 365 13 Test Result Analysis...

Page 366: ...Test Result Analysis 366 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 367: ...are correct and whether the device works as specified The result tools to analyze the device behavior and to detect errors in the setup are discussed in this lesson What you will learn After this les...

Page 368: ...wing result tools Error Map Timing Diagram and Softscope State List In general a testflow is composed of a number testsuites The result tools allow you to analyse the results of a selected testsuite T...

Page 369: ...r a user defined test The Error Map Tool enables you to set up the parameters of the error map for analyzing errors resulting from a test You launch the Error Map as follows 1 Click on the Results tab...

Page 370: ...u Toolbar consists of five different menus Each of these menus contain submenus The menus are useful for navigating through the Error Map User Interface Figure 231 Error Map menu and icon Toolbar Erro...

Page 371: ...bar View Control Area The View Control Area is used to display the error results of the executed test setup The View Control Area consists of the following 4 sections Cycle Entry Field Navigation Area...

Page 372: ...atus Figure 234 Statusbar Using the Detailed Error Map You activate the Detailed Error Map as follows 1 Select a cell in the Overview folder Select Acquisition mode 2 Select Result Acquisition Mode Fo...

Page 373: ...ure Oriented Detailed Error Map allows you to gather failures and save them in the 8K memory of the Error Map The area of focus enlarged cells in the Force Failure Oriented Mode can cover several cell...

Page 374: ...ll the information of the focused cells which includes all failure and all pass data If most of the pins of the test device fail using the Cycle Oriented Detailed Error Map can be faster then using th...

Page 375: ...e from the DUT s outputs The Timing Diagram window has three modes of operation Timing Diagram HighRes Timing Diagram Softscope Using the Timing Diagram You launch the Timing Diagram as follows 1 Clic...

Page 376: ...erest You can select Select expected or Select received to change between the expected and the received waveforms You can use formats to select which pins and groups are displayed NOTE If the mouse cu...

Page 377: ...ous edge settings are used to show all transitions within the analysis window given VOH VOL setting This mode is useful to perform timing measurements with the cursor and the marker Also it makes glit...

Page 378: ...pe mode description In this mode timing and voltage are varied in the region to be displayed producing the equivalent of a scope picture Several functional tests with various level and edge settings a...

Page 379: ...an edge compare at 80 80 ns of a 100 ns period Differences between different modes In the picture you can see the differences For the Timing Diagram one Functional Test is run The display is calculat...

Page 380: ...Double click on the State List icon You see the State List Figure 241 Figure 241 State List State List description The State List looks similar to the vector setup and displays data in exactly the dis...

Page 381: ...t Test Result Analysis Agilent 93000 SOC Series User Training Part 1 October 2004 381 To position the state list on another section of your test scroll the State List to the section If there are no da...

Page 382: ...isplays and the Vector Setup window synchronized For example to analyze the appropriate vector for a failed cycle 1 Select the failed cycle in the Error Map 2 Select Code align displays 3 Change to th...

Page 383: ...383 13 6 Review Test 1 What is the Error Map used for 2 What is the Timing Diagram used for 3 What are the three modes of operation in the Timing Diagram window What are they used for a b c 4 What is...

Page 384: ...Test Result Analysis 13 6 Review Test 384 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 385: ...Agilent 93000 SOC Series User Training Part 1 October 2004 385 14 Device Characterization DC Tests...

Page 386: ...Device Characterization DC Tests 386 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 387: ...dgement This lesson covers two DC testfunctions in more detail Continuity Output DC voltage What you will learn After this lesson you will know and understand the DC test operating principles used by...

Page 388: ...d select the entry DC Tests Figure 243 DC Test Functions Available test functions You can select one of the following test functions Continuity checks for continuity of the test signal paths and for s...

Page 389: ...UT supply currents when the DUT is in a static state DC Resources These test functions use one or more of the tester s DC resources DPS Pin PMU High Precision PMU and Programmable Load to make a measu...

Page 390: ...can be connected to any of these channels The HPPMU provides highest accuracy dc measurements engineering Availability and Relay Matrix of PMUs Availability of PMUs is as follows Per Pin PMU Provided...

Page 391: ...Sequence Per Pin PMU Theory of Operation The hardware of the SOC Series is optimized for highest throughput In order to support this in the domain of DC measurements every digital pin is equipped with...

Page 392: ...converted into a digital value in order to do an analog measurement rather than a pass fail measurement However taking analog readings is not optimized for highest throughput 16 channels share the an...

Page 393: ...of Parallel Pin PMU Measurements Settling of signals costs time However the Pin PMU signals can settle in parallel parallel value measurement saving a lot of settling time Next the Board ADC determin...

Page 394: ...voltage is forced by the PPMU and the current flowing is measured Figure 248 Equivalent Circuit Diagram PPMU in Voltage Force Mode Current Force Mode In the current force mode the PPMU is programmed t...

Page 395: ...s section the clock board contains the High Precision PMU So there is one High Precision PMU on every cardcage The next figure illustrates how the channel boards are connected to the High Precision PM...

Page 396: ...rization DC Tests 14 2 Per Pin PMU and High Precision PMU 396 Agilent 93000 SOC Series User Training Part 1 October 2004 DC Relay The DC relay establishes the connection to a particular channel of the...

Page 397: ...ed to check the chip bonding and connections to the test fixture check protection circuits in the DUT such as input clamp diodes by forcing a current into a device pin and measuring the voltage betwee...

Page 398: ...Enter a value for the pass voltage maximum parameter 7 Enter a settling time if required 8 Select whether you want to measure only with the polarity entered in the test current or to repeat the test w...

Page 399: ...ult for the whole test is failed and the reverse polarity test is not performed If the test passes current flow is reversed Test fail If the reverse measurement fails the result for the whole test is...

Page 400: ...a func tional test to be executed Functional test cycles In order to test one pin the test function executes a functional test consisting of four cycles At all pins except the measured pin during the...

Page 401: ...3 Checking for Continuity and Short Circuits Device Characterization DC Tests Agilent 93000 SOC Series User Training Part 1 October 2004 401 Figure 252 Continuity Test Programmable Load Comparator Lev...

Page 402: ...y for Output DC Measurements Figure 253 illustrates the output DC measurement Table 3 DC Output Voltages for VCC 5 5V Voltage Limit Force Current VOL 0 1V IOL 50 A no load specified VOL 0 44V IOL 24mA...

Page 403: ...OL measurement described above You force for example using a PMU a current IOH according to the device specs on the output pins in logical high state and measure the associated output voltage VOH For...

Page 404: ...he output DC testfunction we include a corresponding testsuite in the testflow Figure 254 Output DC Testsuite in the Testflow Gross functional test The output DC testsuite follows the gross functional...

Page 405: ...nction are defined in the testsuite window We choose the same sets as for the gross functional test Figure 255 Specification of Primary Sets Defining the Testfunction Parameters To define the testfunc...

Page 406: ...easurement with the PPMU 10 20 for the vector range This means that the testfunctions scans the vectors 10 20 of the pattern gross_func for high and low levels occurring at the pins of the pin groups...

Page 407: ...gure 257 Vector Range for Output DC Testfunction So you can see that an optimal use of the parallel test execution capability also requires a corresponding vector sequence Exit and save 7 Click Done i...

Page 408: ...Figure 258 Testsuite Flags to Control the Returned Results Figure 259 shows how to specify the kind of results the testfunction returns Figure 259 Testsuite Flag Settings Returns the maximum value of...

Page 409: ...datalog are determined by the flag settings in the testsuite window Test Execution When you execute the output DC test the following actions take place 1 A functional test is executed It must pass to...

Page 410: ...st is split into two tests The first low level test is performed with the values as set in the LOW column the second high level uses the values set in the HIGH column After selecting Report Mode Test...

Page 411: ...nly low measurement 12 Click on a PMU radio button to select either the High Precision PMU SPMU or the Pin PMU PPMU for the measurement Execute 13 Click the exec button All pins are connected DPS leve...

Page 412: ...uring the Operating Current After selecting Report Mode Test Mode and Repeat Mode as required Enter appropriate values 2 Type in the DPS pins that are to be tested 3 Enter a value for the minimum oper...

Page 413: ...hat ensures the driver is tristated during the time the measurement is made The sequencer is started from the label defined in the Data Manager window After the delay time has elapsed the current flow...

Page 414: ...eep Tests Sweep Tests The test functions in the Sweep Test group are used to produce shmoo plots that show the operating characteristics of the device while varying two input parameters These may be A...

Page 415: ...ned about the Agilent 93000 SOC Series standard test functions regarding the DUT s DC behavior You have learned what test functions are available how the tester s DC resources are used for the tests h...

Page 416: ...Device Characterization DC Tests 14 8 Summary and Discussion 416 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 417: ...system a b 2 Which PMU is provided a once per digital channel b once per 128 digital channels 3 Circle all that apply Which testsuite flag s should be selected to return pass fail results per pin a Ou...

Page 418: ...Device Characterization DC Tests 14 9 Review Test 418 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 419: ...Agilent 93000 SOC Series User Training Part 1 October 2004 419 15 Device Characterization AC Tests...

Page 420: ...Device Characterization AC Tests 420 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 421: ...will have an understanding of the search alog rithms used in device characterization and you will be able to measure the AC electric characteristics and the operating requirements of a given device us...

Page 422: ...s value set in the Test Control window and executing a functional test All value measurements are made by performing a search to find the required AC parameter These searches are based on the function...

Page 423: ...value If a functional test with the primary setting fails no search will be performed and you will receive a warning message The test function always reports the last pass value the resolution of the...

Page 424: ...alfway between the limits and a functional test is run again Depending on whether this passes or fails the param eter moves halfway again in the direction of expected pass fail transi tion This is rep...

Page 425: ...h It starts out as a linear search with typically a fairly large step size When the first fail is found it switches to a binary search to get better resolution on the measurement Advantages always hig...

Page 426: ...t the entry AC Tests Figure 265 AC Test Functions AC test functions There are several groups of AC test functions Functional Test covered in lesson 9 Timing Tests Setup Time Hold Time and Propagation...

Page 427: ...rization AC Tests Agilent 93000 SOC Series User Training Part 1 October 2004 427 Beyond these you may also use the test functions in the SWEEP TEST group to test the device while changing two paramete...

Page 428: ..._volt_sensitivity from the list of AC Tests Figure 262 Testing the Output Voltage Sensitivity After selecting Report Mode Test Mode and Repeat Mode as required Select appropriate values 2 In the pin l...

Page 429: ...alue is selected binary search is used to find the fail region one limit at a time Tester limits 2 to 7V and the nominal levels specified in the level setup are used as boundaries for the binary searc...

Page 430: ...tion delay 1 Select propagation_delay from the list of AC Tests Figure 263 Testing the Propagation Delay After selecting Report Mode Test Mode and Repeat Mode as required Select appropriate values 2 I...

Page 431: ...evice Characterization AC Tests Agilent 93000 SOC Series User Training Part 1 October 2004 431 Execute 6 Click the exec button Linear binary search is performed if there is an edge compare binary sear...

Page 432: ...ing a binary search The standard Propagation Delay test function always uses a linear binary search The measure ment can be done pin by pin serial or for all pins at the same time parallel Select Glob...

Page 433: ...433 6 Select the search range and resolution by entering the start stop and step values Step may be specified in resource units ns V A or as the number of steps between start and stop n The other par...

Page 434: ...eep Tests The test functions in the Sweep Test group are used to produce shmoo plots that show the operating characteristics of the device while varying two input parameters These may be AC and or DC...

Page 435: ...tions regarding the DUT s AC behavior You have learned what test functions are available what search algorithms are used to determine the test results linear binary lin bin how to test the DUT s outpu...

Page 436: ...5 8 Review Test 1 All value measurements are made by performing a search to find the required AC parameter What are the three types of search algo rithm that might be used a b c 2 What manual should y...

Page 437: ...Agilent 93000 SOC Series User Training Part 1 October 2004 437 16 Shmoo Tool...

Page 438: ...Shmoo Tool 438 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 439: ...of the Shmoo Tool features and uses this lesson shows you how to use it to perform typical debugging and char acterization tasks What you will learn After this lesson you will know how to set up and...

Page 440: ...ntation of the test results showing the pass fail result for each coordinate pair that is tested see Figure 266 In this manner you can determine the operational envelope of the DUT for the chosen para...

Page 441: ...oo Spec test function allows you to vary specification vari ables instead of tester resources This will be discussed in HP 93000 SOC Series User Training Part 2 The SOC Series supports traditional 2D...

Page 442: ...number of steps by entering number in the STEP row number is an integer between 1 and 100 You can also specify a test file to be executed with normal timing voltage settings prior to setting paramete...

Page 443: ...Figure 268 green indicates passing and red indicates failing The Shmoo Plot function performs a single test for each x y parameter pair It starts with parameters entered for x and y start values and...

Page 444: ...several different devices under the same condi tions shmoo a 3rd parameter in the overlay axis for example a Pin compare Shmoos using different vector sets mode A shmoo test can be executed in normal...

Page 445: ...s while you set up your shmoo plot Result Information You can obtain the following result information Pass Fail result Global Error Count Counts all errors that occur during shmoo plot execution This...

Page 446: ...region surrounding the line between passed and failed areas First a rough raster of test points is created over the whole area This provides rough information of where the pass fail boundary lies Subs...

Page 447: ...have selected the test mode erct in the Test Control window for the Shmoo Plot the total number of errors for each functional test executed is displayed Figure 270 Example of an Error Count Shmoo Plot...

Page 448: ...for the Shmoo Plot the first cycle number in which the Functional Test failed is displayed This helps you to gain an overall picture of where the test is failing and what is causing the test to fail...

Page 449: ...04 449 Overlaying shmoo plots You can overlay shmoo plots to compare the results from different shmoo tests An example is shown in Figure 272 The green area of the plot passes in both tests the blue a...

Page 450: ...each x y spec parameter pair If you need the equation based test setups to be reeval uated use the Shmoo Spec test function not the Shmoo Plot 2D The same result display modes are available as for th...

Page 451: ...esults This information is stored the directory shmoo residing in your device directory Make sure that you have write access to this direc tory You can now start the SmarTest and launch the Shmoo Tool...

Page 452: ...Figure 274 Shmoo Tool Start up Screen The Shmoo Tool is composed of different pages The Setup Page The Overlay Page Result Pages Setup Screen The setup screen is divided into three main regions X axis...

Page 453: ...is to be incremented or decremented When you click on the arrowhead to the right of the box a Resource Browser appears separate window The Resource Browser contains folders which can be opened to reve...

Page 454: ...addressed by data parameter le leading and data parameter te trailing for example D1 le D1 te Available data parameters The available data parameters are D1 first drive parameter D2 second drive para...

Page 455: ...cycles associ ated with the data parameter you have entered in the Resource entry field Select a device cycle name You can also type the device cycle name directly into the entry field NOTE If you ha...

Page 456: ...elected Pins and Groups on the right hand side Move either individual pins or pin groups from the left hand windows to the right hand window or in the opposite direction by highlighting the pin pin gr...

Page 457: ...specified as a number of measurements Enter the required number in the first field and instead of the units enter Steps in the second field Linear Logarithmic Scale Selection Select either linear and...

Page 458: ...ber 2004 Figure 280 Steps Entry Selection of Axis to be Shmooed First Normally the resource assigned to the X axis are the first to be incre mented It is possible however to select the Y axis to be in...

Page 459: ...ored To compose a list of result pins 1 Click on the arrow by the Result Pins box to obtain the Edit Pinlist window 2 Compose the pin list in the Edit Pinlist window and click ok Result Type Selection...

Page 460: ...and sets the primary sets of that testsuite If you have selected Functional Test this is all you have to do before you start the shmoo If you have selected From Testcontrol Window you want to execute...

Page 461: ...s Set Up Shmoo Tool Agilent 93000 SOC Series User Training Part 1 October 2004 461 NOTE You can use spec parameters in a testfunction However if you shmoo this spec parameter it is not varied in the t...

Page 462: ...Data Setup Menu The Setup menu in the shmoo tool menu bar allows you to both store set up data and retrieve previously stored set up data Loading Stored Set Up Data Sets Select Setup Load to get previ...

Page 463: ...er options from the shmoo tool Setup menu System Default The system default is delivered with the installation tape Device Default The device default has to be defined by the user saving a shmoo setup...

Page 464: ...ss fail transition boundary using a coarse search and then performs high resolution measurements only in the immediate neighborhood of this boundary The advantages and disadvantages of each method are...

Page 465: ...est region Instead a coarse low resolution plot is first made to determine the approximate position of the transition and then the tool performs a high resolution search only within a certain distance...

Page 466: ...e on the result screen panels shown in Figure 286 Figure 286 Result Display Selection Panels The result types available correspond to the result types selected on the setup page before the shmoo plot...

Page 467: ...ursor to the cell You then get a pop up displaying the result information Zoom Region Selection To obtain an enlarged view of a small area of the plot outline the required area to be viewed using the...

Page 468: ...meter value incre ments decrements can now be seen as textual percentage or color changes Comparison of Results The overlay screen can also be used to give a quick indication of differ ences between t...

Page 469: ...ever in this case only the tested cells added to the overlay have an effect on the accumulated results Standard shmoo plot results can be added at any time to the overlay The overlay function keeps tr...

Page 470: ...e varying two input parameters 2 What is the difference between the Global Search function in the last lesson and Sweep Test functions 3 What is a shmoo plot 4 In a shmoo plot why should the parameter...

Page 471: ...ent 93000 SOC Series User Training Part 1 October 2004 471 7 What happens when you select fast mode for a shmoo plot 8 What results can be obtained from the shmoo plot 9 What can you use the overlay s...

Page 472: ...Shmoo Tool 16 10 Overlay Screen 472 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 473: ...Agilent 93000 SOC Series User Training Part 1 October 2004 473 17 Measuring Pin Margins...

Page 474: ...Measuring Pin Margins 474 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 475: ...es the pin margin test can also be used to find a single hardware resource edge or level that can be moved to make a failing device pass What you will learn After this lesson you will be able to run P...

Page 476: ...dge or level that can be moved to make a failing device pass NOTE The margins can only be measured if the functional test with the actual settings passes Only if you suspect a certain pin or pin group...

Page 477: ...With the pin margin tool you can determine just how much headroom you have for each of the following hardware resources tester period edge delays driver levels receive thresholds clamp voltages load c...

Page 478: ...cute the appropriate testsuite This step is optional but it will make setup easier because executing the testsuite loads the primary sets 3 When the Pin Margin window appears set the parameters 4 Exec...

Page 479: ...settings are as follows All used edges pins timing levels sets and level resources vih vil voh vol vch vcl vt ioh iol will be used no period will be used the current testsuite dataset label testfuncti...

Page 480: ...e edge delay chosen exceeds the distance between the edge to be varied and its neighboring edge the edge to be varied will only be shifted until it reaches the neighboring edge Pass fail results are d...

Page 481: ...mary will contain it essentially acts like a filter This summary will be at the end of the test report once you have performed a test 1 Select Summary in the Settings pulldown menu 2 Set up your summa...

Page 482: ...omes to a transition no more points are tested This can be useful as fast check of your pin margin 1 Select Step Mode in the Settings pulldown menu 2 Activate the Only Test to First Transition check b...

Page 483: ...roups or DPS pins on which to perform your pin margin test Figure 293 Pin Selection Menu 2 Select all the appropriate pins groups that will be included in your test If you select Pins a list of all gr...

Page 484: ...4 pops up Figure 294 Specifying DPS Pins This figure shows the default settings For the default settings steps 2 range 5 a margin test is performed for each selected timing and level resource with the...

Page 485: ...same edges The pins of each subset are tested in parallel The margins of such a subset are determined by its worst case pins for the lower and upper margin By Groups option Does the same for each sele...

Page 486: ...ich edges you want to use See Figure 297 Table 5 Specifying Timing Sets Serial Parallel By Groups pins selected S0 S1 DS0 DS1 A margin measurementfor each pin is per formed indepen dent from the pin g...

Page 487: ...l sets highlight the ones you want to use NOTE Independent from your selection only those level sets will be used that are actually used in the vector pattern either as primaries or by changing sets u...

Page 488: ...stsuite with the setups you want to use in your pin margin test 4 Setup and run the margin test 5 Repeat steps 3 and 4 for other testsuites as required 6 In the Pin Margin tool select Save Control Log...

Page 489: ...etup Measuring Pin Margins Agilent 93000 SOC Series User Training Part 1 October 2004 489 Figure 301 Control File Example For more details on the Control Log file including syntax refer to the Results...

Page 490: ...0 Agilent 93000 SOC Series User Training Part 1 October 2004 17 3 Summary and Discussion In this lesson you have learned about the SOC Series Pin Margin Tool If there have been any problems please dis...

Page 491: ...ng Pin Margins Agilent 93000 SOC Series User Training Part 1 October 2004 491 17 4 Review Test 1 What are the parameters measured using the Pin Margin Tool 2 How many combinations of Absolute and Rela...

Page 492: ...Measuring Pin Margins 17 4 Review Test 492 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 493: ...Agilent 93000 SOC Series User Training Part 1 October 2004 493 18 Advanced Testflow Control...

Page 494: ...Advanced Testflow Control 494 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 495: ...ion to directly send firmware commands to the tester What you will learn After this lesson you will be able to use testflow variables Using test flow variables in testfunctions in loops and conditiona...

Page 496: ...pes of Testflow variable There are four different types of testflow variables you can define Double Double A double value Typically such variables take result values of testsuites Userflag Userflag An...

Page 497: ...2 In the window that pops up give the variable s type name and initial value The new variable its initial and its current value are displayed in the Testflow Variables window Implicit variables You ca...

Page 498: ...the values of variables Figure 303 Using Variables in the Continuity Testfunction To refer to a testflow variable in the Test Control window simply enter the name of the variable preceded by an sign f...

Page 499: ...tions and Conditional Branching In general a testflow is composed of different branches The branch a particular testflow takes during test execution may depend on test results of special testsuites Th...

Page 500: ...double in the Testflow Variables window 2 Set the initial values a 0 I_test 20 3 Select Insert Repeat Loop to insert a repeat loop in the testflow Enter if then 4 To include the continuity testsuite i...

Page 501: ...nti nuity test passes initial value is 0 That is this condition reflects the requirement stated above Assign value 7 To set the flag a insert an Assign box in the pass branch of the continuity test se...

Page 502: ...I_test 100 For Loop The for loop will be discussed in the following chapters together with built in functions see Example Unburst Loop on page 505 Conditional Branching In the examples above for the...

Page 503: ...lect Insert print To print the value of a variable to the Report Window select Expression in the Print Dialog window To print a string to the Report Window select String in the Print Dialog window and...

Page 504: ...about Testflow Execution Figure 307 Retrieve Information on Testflow Execution These built in functions allow you to retrieve information on the execu tion of the current testflow They take the name o...

Page 505: ...ividual labels within the burst see the following example There are two built in functions which allow you to access the names of the individual burst labels burstfirst burstlabel burstnext label The...

Page 506: ...bel name of the burst labels You use this variable in the following for loop You define the for loop in the For Loop Dialog box when you insert the for loop in the testflow Assign Expr assigns an init...

Page 507: ...t up But replace the burst in the field Vector Label of the testsuite window by the variable lbl You now have setup a test using the actual setting of the variable lbl always an individual label of th...

Page 508: ...s the value of a level spec variable spst_timing eqnset specset returns 1 if the selected timing specification combination of equa tion and spec set exist otherwise returns 0 spst_level eqnset specset...

Page 509: ...s Although the hardware settings now in general deviate from the original setup the level or timing icons in the Data Manager are not shaded If you do not explicitly reset the spec value to its origin...

Page 510: ...ite The download suite is an optional testsuite that can be used to get an initial setting for the tester If used the settings are downloaded when the test program is loaded If not they are downloaded...

Page 511: ...gets into the pause state This state is either chosen or programmed or occurs in most cases of exception handling tester library or program errors The pause suite is executed before the pause section...

Page 512: ...stprogram Enter dataset or command 2 Enter the dataset or user command to be executed Figure 312 Inserting Special Testsuites You can use these testsuites for example to perform special power up down...

Page 513: ...the following we discuss some examples In an optimized testflow testsuites asking for PASS FAIL results are executed optimized Value tests are executed non optimized This deci sion is always made on t...

Page 514: ...ons Functional tests Functional tests by themselves are already as optimized as they can be DC Test Optimization Figure 314 DC Test Optimization DC tests For DC tests the optimization strategy is base...

Page 515: ...tions The following lists provide information on which test functions can automatically be optimized in which way Table 6 DC Testfunctions Test Function Optimization Expression Support continuity usin...

Page 516: ...ames starting with a followed by ht the testflow name another and the name of the original data set or data set component The optimized versions always exist in parallel with the non optimized version...

Page 517: ...datalogging How to Enter Information on a Testflow 1 Select Select Information Figure 315 Information Window 2 Enter background information on the testflow No restrictions apply to any of these fields...

Page 518: ...ples of this size The global sample size also affects the rules for the single bins 3 Enter the rules for OOC Warning and OOC Pause Test These are similar to the OOC rules for each single bin The OOC...

Page 519: ...appropriate options You can redirect the Report Window to file or printer You can redirect datalogs to file printer or report window You can turn the datalog formatting on off The datalog formatter is...

Page 520: ...specifies after how many reprobe requests for consecutively tested devices the test program will stop with an error condition You can turn the tester status tracking on off monitor You can enable the...

Page 521: ...ther the testflow executes in parallel or in serial for multiple sites You can enable the optimize mode to execute high throughput versions of the testflow You can enable the overon feature to allow t...

Page 522: ...ual Mixed Signal Testing Besides the AC and DC test functions there are four other groups of test functions Other Tests The functions in this group provide high level access to low level resources FW...

Page 523: ...ction allows you to read the state of the utility input lines Set Utility Lines Set Utility Lines This function allows you to set the utility output lines Sequencer Control The functions in this group...

Page 524: ...roup edit box and select the entry Other Tests 4 Select FW_escape from the list of Other Tests Figure 320 Using the Firmware Escape This test function allows you to string together a group of low leve...

Page 525: ...tion Execute 8 Click the exec button The tester state is set as defined and the FW setup command is executed Then the FW execution commands will be executed and repeated according to the set repeat mo...

Page 526: ...Advanced Testflow Control 18 7 Executing Firmware Commands 526 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 527: ...a b c d 2 To refer to a testflow variable named V_force in the test control window what syntax do you need to use 3 What is the built in function that allows you to access the result array of a testf...

Page 528: ...Training Part 1 October 2004 6 Name one test function from the Other Tests group and describe what it is for 7 Name one test function from the Sequencer Control group and describe what it is for 8 Na...

Page 529: ...Agilent 93000 SOC Series User Training Part 1 October 2004 529 19 Histograms...

Page 530: ...Histograms 530 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 531: ...In a production environment this allows you to identify and diagnose significant trends in the performance of the DUT The tool is called up through the Agilent SmarTest Production Test software What...

Page 532: ...am tool will accept data log files from Agilent SmarTest in any of three formats Raw ASCII data GDF Generic Data Format HP 8300 F330 datalog EDF Event Datalogging Format Full details of these data for...

Page 533: ...r to select and configure input data display data and output data Figure 321 User Interfaces to Histogram Tool The main screen contains fields where all these user interfaces are implemented These fie...

Page 534: ...be used and displayed by the Histogram Tool When the data source and type have been selected you can then further define the exact data samples that are used for the statistical calculations and disp...

Page 535: ...n allows you to make all the indi vidual auto adjustments simultaneously Plot Data Selection Plot Control Display Region Selection You can select the range and resolution of the display by entering va...

Page 536: ...is 7 143 Cursor panel A narrow panel in the form of a bar running along the bottom of the Graphic Display The panel contains x y coordinates of the cursor to help you to orientate yourself in the Disp...

Page 537: ...ill initially slow down the tool when it is used See the Results Anal ysis Manual On Line Data for more information To open and Configure the Tool Figure 323 shows an overview of using the Histogram T...

Page 538: ...data type already specified otherwise an error message will be displayed f The histogram tool will now load the data into its memory and display a graph according to the settings made On Line Data a S...

Page 539: ...en looking for data pertaining to per pin measure ments of indirect parameters care must be taken to ensure that the intended data is correctly selected Refer to the Results Analysis Manual for comple...

Page 540: ...ult display mode The histogram display shows a graph where vertical bars for each bin represent the number of counts per bin The range and resolution are either chosen directly by the user or they are...

Page 541: ...The range and reso lution are selected in the same manner as for the population density graph Figure 325 Population Distribution Graph Type Difference This type of display shows the deviation of the...

Page 542: ...device can be compared to each other The overlay feature allows you to do this by storing the outline in blue of a previously selected result display and showing this on the current selection 1 Click...

Page 543: ...19 3 Analyzing the Results Histograms Agilent 93000 SOC Series User Training Part 1 October 2004 543 Figure 327 Overlay Screen...

Page 544: ...inly straight forward calculations using the data extracted from the datalog file To use these results effectively you must have a basic understanding of the applica tion of statistical theory Figure...

Page 545: ...menu window will appear 3 Select Report A Report File Name window appears Enter the required filename with its path in the bottom field or select an existing filename to be overwritten from the browse...

Page 546: ...MaxPeak 5 4675 DeltaPeak 0 007176 Test Statistics Low Limit 1e 99 High Limit 1e 99 Pass 25 Fail 0 Yield 100 00 Cp 1 5859e 101 Cpk 1 5859e 101 To see the histogram properly To see the histogram properl...

Page 547: ...OC Series User Training Part 1 October 2004 547 Figure 329 ASCII Histogram Results 5 46025 5 5 46075 4 5 46125 6 5 46175 2 5 46225 1 5 46275 2 5 46325 0 5 46375 0 5 46425 1 5 46475 1 5 46525 1 5 46575...

Page 548: ...ober 2004 19 4 Summary and Discussion In this lesson you have learned about the SOC Series Histogram Tool functions used to provide statistical data analysis shown in both graphical and text formats I...

Page 549: ...st 1 What format of data log files will the Histogram Tool accept 2 Three types of graph are available for you to display statistical data What are they 3 True or False To see the histogram properly y...

Page 550: ...Histograms 19 5 Review Test 550 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 551: ...Agilent 93000 SOC Series User Training Part 1 October 2004 551 A Appendices...

Page 552: ......

Page 553: ...Agilent 93000 SOC Series User Training Part 1 October 2004 553 B Spec Sheet 74ACT299...

Page 554: ...Spec Sheet 74ACT299 554 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 555: ...Spec Sheet 74ACT299 Agilent 93000 SOC Series User Training Part 1 October 2004 555...

Page 556: ...Spec Sheet 74ACT299 556 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 557: ...Spec Sheet 74ACT299 Agilent 93000 SOC Series User Training Part 1 October 2004 557...

Page 558: ...Spec Sheet 74ACT299 558 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 559: ...Spec Sheet 74ACT299 Agilent 93000 SOC Series User Training Part 1 October 2004 559...

Page 560: ...Spec Sheet 74ACT299 560 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 561: ...Spec Sheet 74ACT299 Agilent 93000 SOC Series User Training Part 1 October 2004 561...

Page 562: ...Spec Sheet 74ACT299 562 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 563: ...Spec Sheet 74ACT299 Agilent 93000 SOC Series User Training Part 1 October 2004 563...

Page 564: ...Spec Sheet 74ACT299 564 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 565: ...Agilent 93000 SOC Series User Training Part 1 October 2004 565 C UNIX Commands...

Page 566: ...UNIX Commands 566 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 567: ...his Lesson Overview To successfully use the Agilent 93000 SOC test system a background in UNIX is necessary This lesson reviews basic usage of UNIX What you will learn After this review you will be ab...

Page 568: ...Command Description Comment find directory name search for files in a directory hierarchy ls list contents of directories ls a shows the contents includes the hidden files ll shortcut for ls l long f...

Page 569: ...of files UNIX has two utilities to accom plish these tasks find and grep find Use find when you are looking for a file based on its filename The syntax for this command is find directory name name fi...

Page 570: ...the file open and allows lines of the file to be written to the display as they are added Archiving Files and Directories If you want to archive files so they are small enough to be stored or transfer...

Page 571: ...isplayed so you can read about the command in more detail Another useful feature is the ability to search for a command to perform a specific task even if you are not sure what the command name is To...

Page 572: ...UNIX Commands 572 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 573: ...Agilent 93000 SOC Series User Training Part 1 October 2004 573 D Linux Commands...

Page 574: ...Linux Commands 574 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 575: ...esson Overview To successfully use the Agilent 93000 SOC test system a background in Linux is necessary This lesson reviews basic usage of Linux commands What you will learn After this review you will...

Page 576: ...user group name group name directory name Set the user of the group to owner of the whole directory structure clear Clear the screen compress file name Compress file cp file directory Copy files expo...

Page 577: ...cols 1000 grep process name pwd Print name of current working directory rm file name Remove files rm rf directory name Remove full directories rmdir directory name Remove directory tar cvf file name t...

Page 578: ...e compiler options please consult your man pages Table 2 HP UX and Linux compiler option differences HP UX cc option Linux gcc option Description Ac traditional Disable ANSI C compliance dynamic fpic...

Page 579: ...formation used by the HP SoftBench static analysis tool Y Enable Native Language Support NLS DCapptype Generate code for portable or embedded applications dfname Specify the profile database to use wi...

Page 580: ...hing else print libgcc file name Equivalent to print file name libgcc a see above print prog name program Print the full name of the program file program that would be used when linking such as cpp Do...

Page 581: ...n H not available Print the name of each header file used in addition to other normal activities I dir I dir Insert the directory specified by dir into the include file search path l library l x Link...

Page 582: ...anything else print search dirs not available Print the name of the configured installa tion directory and a list of program and li brary directories searched for by gcc Do not do anything else Q not...

Page 583: ...ubprocess x ex linker This is a general case For specific exam ples which replace several HP UX compiler options please consult your man pages Wtraditional M Provides ANSI migration warnings that ex p...

Page 584: ...Linux Commands 584 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 585: ...Agilent 93000 SOC Series User Training Part 1 October 2004 585 E Using vi...

Page 586: ...Using vi 586 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 587: ...PAD Basic vi commands Opening the vi Editor vi file name opens the vi editor from the UNIX command line Closing a File and Saving Changes w saves a file wq saves file and exits the vi editor q exits t...

Page 588: ...er after cursor Numbering Lines set nu numbers lines set nonu removes line numbers Alternative to vi DTPAD OPTIONAL If you have trouble using vi you can use a different editor such as the built in GUI...

Page 589: ...Agilent 93000 SOC Series User Training Part 1 October 2004 589 F Pin Margin Algorithm...

Page 590: ...Pin Margin Algorithm 590 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 591: ...margin test does not characterize your DUT To characterize the DUT you should use other tools like the Shmoo Tool or the test functions The pin margin test characterizes the tester and the test progr...

Page 592: ...argin tool you can determine just how much headroom you have for each of the following hardware resources tester period edge delays driver levels receive thresholds clamp voltages load currents termin...

Page 593: ...ransition below the actual value the following is carried out a a binary search is performed see Binary Search Algorithm on page 595 and the actual fail value obtained b a functional test is performed...

Page 594: ...performed starting from the actual value in the direc tion of the lower limit until a fail is encountered A measurement is then performed starting from the actual value in the direction of the upper...

Page 595: ...ns will not be detected Binary Search Algorithm The binary search algorithm uses a constantly reducing search region to limit the number of measurements required for each search This is illustrated in...

Page 596: ...ing the distance to the limit before performing another test If no transition is detected it continues in the same direction and halves the distance to the limit where it performs another test It cont...

Page 597: ...Agilent 93000 SOC Series User Training Part 1 October 2004 597 G System File Examples...

Page 598: ...System File Examples 598 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 599: ...art of the system that tells the system what resources are available what items are licensed what your tester speed is and so on The level and timing files provide information on the level and timing...

Page 600: ...System File Examples 600 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 601: ...I O1 I O0 TERM 1 OFF CP DS7 DS0 S1 S0 _MR Q7 Q0 I O7 I O6 I O5 I O4 I O3 I O2 I O1 I O0 TERM 2 OFF CP DS7 DS0 S1 S0 _MR TERM 2 T 2500 Q7 Q0 TERM 2 OFF I O7 I O6 I O5 I O4 I O3 I O2 I O1 I O0 TERM 3 O...

Page 602: ...SET 2 5V with termination derived from level set 2 PINS ctrl ser_in vil 0 vih 4 8 PINS ser_out vol 2 4 voh 2 6 vt 2 5 PINS io_in vil 0 vih 4 8 vol 2 4 voh 2 6 LEVELSET 3 5V active load derived from le...

Page 603: ...Pins declaration vout VCC ilimit 1000 t_ms 4 offcurr act LEVELSET 1 no termination first Level Set without termination PINS ctrl ser_in pin declaration vil VIL vih VIH PINS ser_out vol VOL voh VOH PIN...

Page 604: ...t VOL VOH 2 iol 24 ioh 24 PINS io_in vil VIL vih VIH vol VOL voh VOH vt VOL VOH 2 iol 24 ioh 24 EQSP LEV SPS 9000001619 EQNSET 1 no equations or specs SPECSET 1 generated SPECNAME ACTUAL MINIMUM MAXIM...

Page 605: ...s User Training Part 1 October 2004 605 SPECNAME ACTUAL MINIMUM MAXIMUM UNITS COMMENT VCC 5 V VIL 0 V VIH 4 8 V VOL 2 4 V VOH 2 6 V SPECSET 3 Vcc 5 5V SPECNAME ACTUAL MINIMUM MAXIMUM UNITS COMMENT VCC...

Page 606: ...I O6 I O5 I O4 I O3 I O2 I O1 I O0 WAVE 1 1 F00 2 CP DS7 DS0 S1 S0 _MR WAVE 1 0 FX 2 Q7 Q0 WAVE 1 0 F0Z F1 2 I O7 I O6 I O5 I O4 I O3 I O2 I O1 I O0 WAVE 1 1 F10 3 CP DS7 DS0 S1 S0 _MR WAVE 1 1 F0 3 Q...

Page 607: ...ns physical waveform index D1 D2 E1 E2 BWDS edge actions DCDF device cycle name logical waveform index Drive edges are d1 d2 d3 d4 d5 d6 d7 d8 Drive edges can be specified in any order Tri state is av...

Page 608: ...ndow open for high compare WM window open for intermediate compare WX window open for don t care WU window open for unstable compare WC window close must follow each of the above window opens WAVETBL...

Page 609: ...gnals only This wavetable gets used for relaxed functional verification and using Device Cycle names Phy Waveform Edge Device Cycle Indices Actions Names PINS CP 0 d1 0 d2 0 0 1 d1 1 d2 0 1 brk PINS _...

Page 610: ...Cycle Indices Actions Names PINS CP 0 d1 0 d2 0 0 1 d1 1 d2 0 1 brk PINS _MR 0 d1 0 d2 1 0 1 d1 1 d2 1 1 brk PINS mode 0 d1 1 d2 0 d3 1 SBC_0 1 d1 0 d2 1 d3 0 SBC_1 2 d1 0 DNRZ_0 3 d1 1 DNRZ_1 brk d1...

Page 611: ...2 0 3 1 BWDS d1 F00 DCDF DNRZ 1 DCDF SBC 0 PINS mode ser_in WFDS 0 d1 C11 d2 D11 d3 C11 0 0 1 1 WFDS 1 d1 D11 2 0 3 1 BWDS DCDF DNRZ 1 DCDF SBC 0 PINS _MR WFDS 0 d1 D11 d2 F1N 0 0 1 1 WFDS 1 d1 D11 d...

Page 612: ...1 EE1 5 0 X 6 F0Z L 7 F0Z H 8 F0Z X 9 1 X BWDS DCDF DNRZ 1 DCDF SBC 0 WAVETBL gross_func_wtb multi DISPLAY multi DCDT std PINS CP WFDS0 d1 0 0 WFDS 1 d1 1 d2 0 1 BWDS DCDF 0 DCDF p 1 PINS _MR WFDS 0 d...

Page 613: ...1 0 F00 X 1 F10 X WFDS 1 d1 F0Z r1 EE1 2 L 3 H 4 X BWDS DCDF i 0 DCDF o 1 PINS ser_out WFDS 0 r1 EE1 0 L 1 H 2 X DCDF o 0 WAVETBL gross_func_wtb classic DISPLAY classic DCDT std PINS CP WFDS0 d1 D11 d...

Page 614: ...Z L 3 F0Z H 4 F0Z X BWDS DCDF std 0 PINS ser_out WFDS 0 r1 EE1 0 L 1 H 2 X DCDF std 0 WAVETBL gross_func_wtb single DISPLAY single DCDT std PINS CP WFDS0 d1 D11 d2 0 0 0 1 1 WFDS 1 2 BWDS DCDF std0 DC...

Page 615: ...F0Z H 4 F0Z X WFDS1 5 BWDS DCDF std 0 DCDF reset 1 PINS ser_out WFDS 0 r1 EE1 0 L 1 H 2 X WFDS 1 3 DCDF std 0 DCDF reset 1 WAVETBL PhysIndices This table is for debugging purposes only It uses physic...

Page 616: ...le equation setup to be used with the gross_func wavetable No spec variables and no equations are used All I O pin resources are directly programmed with fixed values SPECS tpdIOx ns TIMINGSET 1 20MHz...

Page 617: ...d2 12 PINS ser_in d1 1 d2 12 PINS _MR d1 0 d2 8 PINS ser_out r1 21 5 PINS io_pins d1 1 r1 7 tpdIOx Added tpdIOx here later EQNSET 2 specs_search_eqn SPECS Spec Unit variables f MHz ts_Sx_CP ns th_CP_...

Page 618: ...ts_Sx_CP ComplDelay d2 CP_ref ts_Sx_CP d3 CP_ref th_CP_Sx PINS ser_in d1 CP_ref ts_DSx_CP ComplDelay d2 CP_ref ts_DSx_CP d3 CP_ref th_CP_Sx PINS _MR d1 CP_ref trec_MR_CP tw_MR d2 CP_ref trec_MR_CP PI...

Page 619: ...d1 1 d2 3 d3 11 PINS _MR d1 3 5 d2 7 PINS ser_out r1 22 PINS io_in d1 4 d2 6 d3 11 2 r1 22 EQSP TIM SPS 9000002516 EQNSET 1 gross_func_eqn WAVETBL gross_func_wtb classic CHECK all SPECSET 3 gross_fun...

Page 620: ..._wtb CHECK all SPECSET 1 gross_func_specs SPECNAME ACTUAL MINIMUM MAXIMUM UNITS COMMENT tpdIOx 0 ns EQNSET 2 specs_search_eqn WAVETBL spec_search_wtb CHECK all SPECSET 1 spec_search_specs SPECNAME ACT...

Page 621: ...04 621 WAVETBL gross_func_devcyc_wtb CHECK all SPECSET 2 gross_func_devcyc_specs SPECNAME ACTUAL MINIMUM MAXIMUM UNITS COMMENT tpdIOx 2 5 ns EQNSET 3 generated_eqnset WAVETBL spec_search_logical CHECK...

Page 622: ...t hp93000 soc calibration std__ This file is for all System Calibration except Analog 2 var opt hp93000 soc calibration std__analog This file is for Analog Instrument Calibration only Two sets of Cali...

Page 623: ...ll path to execute HPSmarTest Related Files PATH PATH opt hp93000 soc prod_env bin PATH PATH opt hp93000 soc com lbin PATH PATH opt hp93000 soc pws bin PATH PATH opt hp93000 soc pws data PATH PATH opt...

Page 624: ...the workorder production Contents of the etc opt hp93000 soc org file is as follows DUT_PATH training s1 INSTALLED_DUT_PATH training s1 Searches recursively for devices starting from the specified dir...

Page 625: ...er 2004 625 Device In Use File A temporary file device_inuse_soc is created under the user s home directory while running SmarTest that points to the current device in use When the SmarTest software i...

Page 626: ...2 Checks if there is no syntax error or feature dependency error in the model file 3 Sets the configuration of the test system from the model file contents The model file is used to simulate the test...

Page 627: ...ration overwrites the model file definition Syntax definition Text after a until end of line is ignored In the following syntax diagram keywords are shown in upper case although the actual case is ign...

Page 628: ...F330 SOC EXHIBITION hpib_interface HPIB hpib interface name See your HP Standard Instrument Control Library SICL manual for valid hpib interface names Examples HPIB hpib Default if entry is missing se...

Page 629: ...s_type GPDPS HVDPS EDPS HP6621A HP6622A HP6623A HP6624A HP6625A HP6626A HP6628A HP6629A HP6632A HP6633A HP6634A HP6651A HP6652A HP6653A HP6654A hpib_addr 0 31 osc integer osc_type HP54 digit digit dig...

Page 630: ...evid 2 addr 18 name DTS2077 SOCGPIB type TIA devid 3 addr 19 name DTS2077 SOCGPIB type TIA devid 4 addr 20 name DTS2077 SOCGPIB type WGC devid 1 addr 22 name AWG610 option 192 168 0 2 255 255 255 0 19...

Page 631: ...Agilent 93000 SOC Series User Training Part 1 October 2004 631 Appendix HList of Abbreviations...

Page 632: ...List of Abbreviations 632 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 633: ...DUT Device Under Test DVM Digital Volt Meter GUI Graphical User Interface HPPMU High Precision PMU ICU Integrated Calibration Unit LE Leading Edge LSB Least Significant Bit MSB Most Significant Bit OO...

Page 634: ...List of Abbreviations 634 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 635: ...Agilent 93000 SOC Series User Training Part 1 October 2004 635 I Third Party Contact Information...

Page 636: ...Third Party Contact Information 636 Agilent 93000 SOC Series User Training Part 1 October 2004...

Page 637: ...Contact Information 637 Agilent 93000 SOC Series User Training Part 1 October 2004 In this Lesson Overview This is contact information for third party vendors who provide funda mental classes for digi...

Page 638: ...Third Party Contact Information 638 Agilent 93000 SOC Series User Training Part 1 October 2004 Third Party Contact Information Soft Test Inc www soft test com Giga Test Labs www gigatest com...

Page 639: ...239 Device Cycle Names 199 user defined 266 Digital Compare block 146 Directories 568 Directory Structure 77 Disconnect button 65 Disconnect State 150 Display Modes 230 Download Suite 510 DPS Board 4...

Page 640: ...rTest 62 Single Mode 231 Spec Set 207 Spec Tool 155 164 Standby button 42 Start SmarTest 61 Start up Screen 62 State List 380 Statusbar 372 step mode measurements pin margin tool 594 Study Materials 1...

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