Agilent Technologies 93000 SOC Series, Training Manual

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Defining the Levels 8-1 AC Levels
146
Agilent 93000 SOC Series User Training Part 1, October 2004
Comparing Output Signals
Comparator The Comparator receives the output signals of the DUT’s o and io pins.
It generates a high/low level compare signal (difference of the actual
signal of the DUT and the high/low compare thresholds vol and voh
specified in the level setup). The Level Generator provides the compare
thresholds to the comparator.
Data Sampler The Data Sampler on the test processor receives the compare signal
from the comparator. It works in two modes:
• Edge compare mode
• Window compare mode
Depending on what you have set up in your timing setup an edge
compare or a window compare is performed.
N O T E
How to set up the compare modes is described in Lesson 7 and
Lesson 8 .
Edge Generator
In the case of an edge compare the Edge Generator triggers the Data
Sample to sample the compare signal at the point in time specified for
the edge compare. The Window Formatter is not needed in case of an
edge compare.
Window Formatter
In case of a window compare the Data Sampler monitors the compare
signal (received from the comparator) in a time window for any transi-
tions. The time window is opened and closed by the Window Formatter
which receives the corresponding timing information from the Edge
Generator.
Digital Compare block
The Data Sampler outputs CMOS signals to the Digital Compare block
for further digital data processing.
Setup Data Required
You specify the compare levels (voh, vol) and the corresponding timing
for the various o and io pins in the setup part of the SmarTest software
(pin configuration, level setup, timing setup and vector setup).
Active Load
Setup Data Required for Specifying Loads
You specify the load currents (iol, ioh) and the commutation voltage
(vt) in the level setup