８３
Table 28
: SATA Insertion Loss Budge
SATA Gen 1 Insertion Loss Budget, 1.5 GHz
Segment
Loss (dB)
Notes
L
A
1.26 Up to 3.0 inches of module trace @ 0.28 dB / GHz / inch
Coupling Caps
0.40
L
B
0.25 COM Express
TM
connector at 1.5 GHz measured value
L
C
3.07 Up to 7.2 inches of Carrier Board trace @ 0.28 dB / GHz / inch
L
D
6.00 Source specification cable and cable connector allowance
Total
10.98
SATA Gen 2 Insertion Loss Budget, 3.0 GHz
Segment
Loss (dB)
Notes
L
A
1.68 Up to 2.0 inches of module trace @ 0.28 dB / GHz / inch
Coupling Caps
0.40
L
B
0.38 COM Express
TM
connector at 3.0 GHz measured value
L
C
2.52 Up to 3.0 inches of Carrier Board trace @ 0.28 dB / GHz / inch
L
D
6.00 Source specification cable and cable connector allowance
Total
10.98
2.9.2.1 General SATA Routing Guidelines
Use the following general routing and placement guidelines when laying out a new design.
• SATA signals must be ground referenced. If changing reference plane is completely unavoidable (that
is, ground reference to power reference), proper placement of stitching caps can minimize the adverse
effects of EMI and signal quality performance caused by reference plane change. Stitching capacitors
are smallvalued capacitors (1 μF or lower in value) that bridge the power and ground planes close to
where a high-speed signal changes layers. Stitching caps provide a high frequency current return path
between different reference planes. They minimize the impedance discontinuity and current loop area
that crossing different reference planes created. The maximum number allowed for SATA to change
reference plane is one.
• Route all traces over continuous GND planes, with no interruptions. Avoid crossing over anti-etch if at
all possible. Any discontinuity or split in the ground plane can cause signal reflections and should be
avoided.
• Minimize layer changes. If a layer change is necessary, ensure that trace matching for either transmit
or receive pair occurs within the same layer. Intel recommends to use SATA vias as seldom as
possible.
• DO NOT route SATA traces under power connectors, other interface connectors, crystals, oscillators,
clock synthesizers, magnetic devices or ICs that use and/or duplicate clocks.
• DO NOT place stubs, test points, test vias on the route to minimize reflection. Utilize vias and
connector pads as test points instead.
