１１
1.3 Reference Documents
Document
PICMGR COM.0 Revision 3.0 COM Express Base Specification,
2017
’
03
’
31 Final
Intel EDS Document
Intel Layout Guide Document
ATX12V Power Supply Design Guide Rev. 2.01
1.4 Revision History
Revision
Date
PCB Rev. Changes
0.10
2017’02’14
A101-1
1.00
2017’10’02
A101-2
1.
Change NC-SI interface connection from 10G to GbE0
& add GbE0 SDP Pin connection to B2B Conn.
2. Remove 10GB NC-SI connection to B2B Conn.
1.10
2018’03’02
A101-2
1. Modify AC coupling cap of the PCIe BUS.
1.20
09 25, 2018
A101-2
1.
Modify LPC Clock output to 24MHz.
